mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0935540232
of_device_id is always used as const. (See driver.of_match_table and open firmware functions) Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Mark Brown <broonie@kernel.org>
505 lines
12 KiB
C
505 lines
12 KiB
C
/*
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* Copyright (c) 2008-2014 STMicroelectronics Limited
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*
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* Author: Angus Clark <Angus.Clark@st.com>
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* Patrice Chotard <patrice.chotard@st.com>
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* Lee Jones <lee.jones@linaro.org>
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*
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* SPI master mode controller driver, used in STMicroelectronics devices.
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*
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* May be copied or modified under the terms of the GNU General Public
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* License Version 2.0 only. See linux/COPYING for more information.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/of_irq.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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/* SSC registers */
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#define SSC_BRG 0x000
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#define SSC_TBUF 0x004
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#define SSC_RBUF 0x008
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#define SSC_CTL 0x00C
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#define SSC_IEN 0x010
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#define SSC_I2C 0x018
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/* SSC Control */
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#define SSC_CTL_DATA_WIDTH_9 0x8
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#define SSC_CTL_DATA_WIDTH_MSK 0xf
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#define SSC_CTL_BM 0xf
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#define SSC_CTL_HB BIT(4)
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#define SSC_CTL_PH BIT(5)
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#define SSC_CTL_PO BIT(6)
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#define SSC_CTL_SR BIT(7)
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#define SSC_CTL_MS BIT(8)
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#define SSC_CTL_EN BIT(9)
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#define SSC_CTL_LPB BIT(10)
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#define SSC_CTL_EN_TX_FIFO BIT(11)
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#define SSC_CTL_EN_RX_FIFO BIT(12)
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#define SSC_CTL_EN_CLST_RX BIT(13)
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/* SSC Interrupt Enable */
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#define SSC_IEN_TEEN BIT(2)
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#define FIFO_SIZE 8
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struct spi_st {
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/* SSC SPI Controller */
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void __iomem *base;
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struct clk *clk;
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struct device *dev;
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/* SSC SPI current transaction */
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const u8 *tx_ptr;
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u8 *rx_ptr;
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u16 bytes_per_word;
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unsigned int words_remaining;
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unsigned int baud;
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struct completion done;
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};
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static int spi_st_clk_enable(struct spi_st *spi_st)
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{
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/*
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* Current platforms use one of the core clocks for SPI and I2C.
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* If we attempt to disable the clock, the system will hang.
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*
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* TODO: Remove this when platform supports power domains.
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*/
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return 0;
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return clk_prepare_enable(spi_st->clk);
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}
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static void spi_st_clk_disable(struct spi_st *spi_st)
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{
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/*
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* Current platforms use one of the core clocks for SPI and I2C.
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* If we attempt to disable the clock, the system will hang.
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*
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* TODO: Remove this when platform supports power domains.
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*/
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return;
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clk_disable_unprepare(spi_st->clk);
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}
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/* Load the TX FIFO */
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static void ssc_write_tx_fifo(struct spi_st *spi_st)
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{
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unsigned int count, i;
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uint32_t word = 0;
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if (spi_st->words_remaining > FIFO_SIZE)
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count = FIFO_SIZE;
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else
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count = spi_st->words_remaining;
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for (i = 0; i < count; i++) {
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if (spi_st->tx_ptr) {
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if (spi_st->bytes_per_word == 1) {
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word = *spi_st->tx_ptr++;
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} else {
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word = *spi_st->tx_ptr++;
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word = *spi_st->tx_ptr++ | (word << 8);
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}
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}
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writel_relaxed(word, spi_st->base + SSC_TBUF);
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}
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}
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/* Read the RX FIFO */
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static void ssc_read_rx_fifo(struct spi_st *spi_st)
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{
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unsigned int count, i;
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uint32_t word = 0;
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if (spi_st->words_remaining > FIFO_SIZE)
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count = FIFO_SIZE;
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else
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count = spi_st->words_remaining;
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for (i = 0; i < count; i++) {
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word = readl_relaxed(spi_st->base + SSC_RBUF);
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if (spi_st->rx_ptr) {
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if (spi_st->bytes_per_word == 1) {
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*spi_st->rx_ptr++ = (uint8_t)word;
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} else {
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*spi_st->rx_ptr++ = (word >> 8);
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*spi_st->rx_ptr++ = word & 0xff;
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}
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}
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}
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spi_st->words_remaining -= count;
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}
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static int spi_st_transfer_one(struct spi_master *master,
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struct spi_device *spi, struct spi_transfer *t)
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{
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struct spi_st *spi_st = spi_master_get_devdata(master);
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uint32_t ctl = 0;
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/* Setup transfer */
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spi_st->tx_ptr = t->tx_buf;
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spi_st->rx_ptr = t->rx_buf;
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if (spi->bits_per_word > 8) {
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/*
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* Anything greater than 8 bits-per-word requires 2
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* bytes-per-word in the RX/TX buffers
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*/
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spi_st->bytes_per_word = 2;
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spi_st->words_remaining = t->len / 2;
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} else if (spi->bits_per_word == 8 && !(t->len & 0x1)) {
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/*
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* If transfer is even-length, and 8 bits-per-word, then
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* implement as half-length 16 bits-per-word transfer
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*/
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spi_st->bytes_per_word = 2;
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spi_st->words_remaining = t->len / 2;
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/* Set SSC_CTL to 16 bits-per-word */
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ctl = readl_relaxed(spi_st->base + SSC_CTL);
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writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
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readl_relaxed(spi_st->base + SSC_RBUF);
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} else {
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spi_st->bytes_per_word = 1;
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spi_st->words_remaining = t->len;
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}
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reinit_completion(&spi_st->done);
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/* Start transfer by writing to the TX FIFO */
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ssc_write_tx_fifo(spi_st);
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writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
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/* Wait for transfer to complete */
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wait_for_completion(&spi_st->done);
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/* Restore SSC_CTL if necessary */
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if (ctl)
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writel_relaxed(ctl, spi_st->base + SSC_CTL);
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spi_finalize_current_transfer(spi->master);
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return t->len;
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}
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static void spi_st_cleanup(struct spi_device *spi)
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{
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int cs = spi->cs_gpio;
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if (gpio_is_valid(cs))
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devm_gpio_free(&spi->dev, cs);
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}
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/* the spi->mode bits understood by this driver: */
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#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
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static int spi_st_setup(struct spi_device *spi)
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{
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struct spi_st *spi_st = spi_master_get_devdata(spi->master);
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u32 spi_st_clk, sscbrg, var;
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u32 hz = spi->max_speed_hz;
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int cs = spi->cs_gpio;
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int ret;
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if (!hz) {
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dev_err(&spi->dev, "max_speed_hz unspecified\n");
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return -EINVAL;
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}
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if (!gpio_is_valid(cs)) {
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dev_err(&spi->dev, "%d is not a valid gpio\n", cs);
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return -EINVAL;
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}
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if (devm_gpio_request(&spi->dev, cs, dev_name(&spi->dev))) {
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dev_err(&spi->dev, "could not request gpio:%d\n", cs);
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return -EINVAL;
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}
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ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH);
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if (ret)
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return ret;
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spi_st_clk = clk_get_rate(spi_st->clk);
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/* Set SSC_BRF */
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sscbrg = spi_st_clk / (2 * hz);
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if (sscbrg < 0x07 || sscbrg > BIT(16)) {
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dev_err(&spi->dev,
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"baudrate %d outside valid range %d\n", sscbrg, hz);
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return -EINVAL;
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}
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spi_st->baud = spi_st_clk / (2 * sscbrg);
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if (sscbrg == BIT(16)) /* 16-bit counter wraps */
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sscbrg = 0x0;
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writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
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dev_dbg(&spi->dev,
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"setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
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hz, spi_st->baud, sscbrg);
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/* Set SSC_CTL and enable SSC */
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var = readl_relaxed(spi_st->base + SSC_CTL);
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var |= SSC_CTL_MS;
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if (spi->mode & SPI_CPOL)
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var |= SSC_CTL_PO;
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else
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var &= ~SSC_CTL_PO;
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if (spi->mode & SPI_CPHA)
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var |= SSC_CTL_PH;
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else
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var &= ~SSC_CTL_PH;
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if ((spi->mode & SPI_LSB_FIRST) == 0)
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var |= SSC_CTL_HB;
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else
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var &= ~SSC_CTL_HB;
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if (spi->mode & SPI_LOOP)
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var |= SSC_CTL_LPB;
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else
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var &= ~SSC_CTL_LPB;
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var &= ~SSC_CTL_DATA_WIDTH_MSK;
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var |= (spi->bits_per_word - 1);
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var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
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var |= SSC_CTL_EN;
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writel_relaxed(var, spi_st->base + SSC_CTL);
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/* Clear the status register */
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readl_relaxed(spi_st->base + SSC_RBUF);
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return 0;
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}
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/* Interrupt fired when TX shift register becomes empty */
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static irqreturn_t spi_st_irq(int irq, void *dev_id)
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{
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struct spi_st *spi_st = (struct spi_st *)dev_id;
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/* Read RX FIFO */
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ssc_read_rx_fifo(spi_st);
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/* Fill TX FIFO */
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if (spi_st->words_remaining) {
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ssc_write_tx_fifo(spi_st);
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} else {
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/* TX/RX complete */
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writel_relaxed(0x0, spi_st->base + SSC_IEN);
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/*
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* read SSC_IEN to ensure that this bit is set
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* before re-enabling interrupt
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*/
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readl(spi_st->base + SSC_IEN);
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complete(&spi_st->done);
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}
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return IRQ_HANDLED;
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}
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static int spi_st_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct spi_master *master;
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struct resource *res;
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struct spi_st *spi_st;
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int irq, ret = 0;
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u32 var;
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master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
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if (!master)
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return -ENOMEM;
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master->dev.of_node = np;
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master->mode_bits = MODEBITS;
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master->setup = spi_st_setup;
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master->cleanup = spi_st_cleanup;
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master->transfer_one = spi_st_transfer_one;
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master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
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master->auto_runtime_pm = true;
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master->bus_num = pdev->id;
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spi_st = spi_master_get_devdata(master);
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spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
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if (IS_ERR(spi_st->clk)) {
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dev_err(&pdev->dev, "Unable to request clock\n");
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return PTR_ERR(spi_st->clk);
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}
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ret = spi_st_clk_enable(spi_st);
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if (ret)
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return ret;
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init_completion(&spi_st->done);
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/* Get resources */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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spi_st->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(spi_st->base)) {
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ret = PTR_ERR(spi_st->base);
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goto clk_disable;
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}
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/* Disable I2C and Reset SSC */
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writel_relaxed(0x0, spi_st->base + SSC_I2C);
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var = readw_relaxed(spi_st->base + SSC_CTL);
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var |= SSC_CTL_SR;
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writel_relaxed(var, spi_st->base + SSC_CTL);
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udelay(1);
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var = readl_relaxed(spi_st->base + SSC_CTL);
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var &= ~SSC_CTL_SR;
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writel_relaxed(var, spi_st->base + SSC_CTL);
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/* Set SSC into slave mode before reconfiguring PIO pins */
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var = readl_relaxed(spi_st->base + SSC_CTL);
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var &= ~SSC_CTL_MS;
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writel_relaxed(var, spi_st->base + SSC_CTL);
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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dev_err(&pdev->dev, "IRQ missing or invalid\n");
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ret = -EINVAL;
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goto clk_disable;
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}
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ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
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pdev->name, spi_st);
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if (ret) {
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dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
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goto clk_disable;
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}
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/* by default the device is on */
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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platform_set_drvdata(pdev, master);
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register master\n");
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goto clk_disable;
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}
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return 0;
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clk_disable:
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spi_st_clk_disable(spi_st);
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return ret;
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}
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static int spi_st_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct spi_st *spi_st = spi_master_get_devdata(master);
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spi_st_clk_disable(spi_st);
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pinctrl_pm_select_sleep_state(&pdev->dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int spi_st_runtime_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct spi_st *spi_st = spi_master_get_devdata(master);
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writel_relaxed(0, spi_st->base + SSC_IEN);
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pinctrl_pm_select_sleep_state(dev);
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spi_st_clk_disable(spi_st);
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return 0;
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}
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static int spi_st_runtime_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct spi_st *spi_st = spi_master_get_devdata(master);
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int ret;
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ret = spi_st_clk_enable(spi_st);
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pinctrl_pm_select_default_state(dev);
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return ret;
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}
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#endif
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#ifdef CONFIG_PM_SLEEP
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static int spi_st_suspend(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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int ret;
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ret = spi_master_suspend(master);
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if (ret)
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return ret;
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return pm_runtime_force_suspend(dev);
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}
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static int spi_st_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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int ret;
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ret = spi_master_resume(master);
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if (ret)
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return ret;
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return pm_runtime_force_resume(dev);
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}
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#endif
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static const struct dev_pm_ops spi_st_pm = {
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SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
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SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
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};
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static const struct of_device_id stm_spi_match[] = {
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{ .compatible = "st,comms-ssc4-spi", },
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{},
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};
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MODULE_DEVICE_TABLE(of, stm_spi_match);
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static struct platform_driver spi_st_driver = {
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.driver = {
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.name = "spi-st",
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.pm = &spi_st_pm,
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.of_match_table = of_match_ptr(stm_spi_match),
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},
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.probe = spi_st_probe,
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.remove = spi_st_remove,
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};
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module_platform_driver(spi_st_driver);
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MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
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MODULE_DESCRIPTION("STM SSC SPI driver");
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MODULE_LICENSE("GPL v2");
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