Palmer Dabbelt 18856604b3 RISC-V: Clear load reservations while restoring hart contexts ... This is almost entirely a comment. The bug is unlikely to manifest on existing hardware because there is a timeout on load reservations, but manifests on QEMU because there is no timeout. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-10-01 13:16:40 -07:00
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boot	riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes	2019-09-20 08:37:24 -07:00
configs	RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig	2019-09-19 05:44:35 -07:00
include	RISC-V: Clear load reservations while restoring hart contexts	2019-10-01 13:16:40 -07:00
kernel	RISC-V: Clear load reservations while restoring hart contexts	2019-10-01 13:16:40 -07:00
lib	riscv: Using CSR numbers to access CSRs	2019-08-30 11:04:19 -07:00
mm	riscv: move the TLB flush logic out of line	2019-09-05 01:54:51 -07:00
net	bpf, riscv: Enable zext optimization for more RV64G ALU ops	2019-07-05 23:55:41 +02:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: make mmap allocation top-down by default	2019-09-24 15:54:12 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: select SiFive platform drivers with SOC_SIFIVE	2019-07-01 13:20:01 -07:00
Makefile	Kbuild updates for v5.4	2019-09-20 08:36:47 -07:00