linux_dsm_epyc7002/drivers/pci
Bharat Kumar Gogada 181fa434d0 PCI: xilinx-nwl: Fix Multi MSI data programming
According to the PCI Local Bus specification Revision 3.0,
section 6.8.1.3 (Message Control for MSI), endpoints that
are Multiple Message Capable as defined by bits [3:1] in
the Message Control for MSI can request a number of vectors
that is power of two aligned.

As specified in section 6.8.1.6 "Message data for MSI", the Multiple
Message Enable field (bits [6:4] of the Message Control register)
defines the number of low order message data bits the function is
permitted to modify to generate its system software allocated
vectors.

The MSI controller in the Xilinx NWL PCIe controller supports a number
of MSI vectors specified through a bitmap and the hwirq number for an
MSI, that is the value written in the MSI data TLP is determined by
the bitmap allocation.

For instance, in a situation where two endpoints sitting on
the PCI bus request the following MSI configuration, with
the current PCI Xilinx bitmap allocation code (that does not
align MSI vector allocation on a power of two boundary):

Endpoint #1: Requesting 1 MSI vector - allocated bitmap bits 0
Endpoint #2: Requesting 2 MSI vectors - allocated bitmap bits [1,2]

The bitmap value(s) corresponds to the hwirq number that is programmed
into the Message Data for MSI field in the endpoint MSI capability
and is detected by the root complex to fire the corresponding
MSI irqs. The value written in Message Data for MSI field corresponds
to the first bit allocated in the bitmap for Multi MSI vectors.

The current Xilinx NWL MSI allocation code allows a bitmap allocation
that is not a power of two boundaries, so endpoint #2, is allowed to
toggle Message Data bit[0] to differentiate between its two vectors
(meaning that the MSI data will be respectively 0x0 and 0x1 for the two
vectors allocated to endpoint #2).

This clearly aliases with the Endpoint #1 vector allocation, resulting
in a broken Multi MSI implementation.

Update the code to allocate MSI bitmap ranges with a power of two
alignment, fixing the bug.

Fixes: ab597d35ef ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller")
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
2019-06-26 10:56:51 +01:00
..
controller PCI: xilinx-nwl: Fix Multi MSI data programming 2019-06-26 10:56:51 +01:00
endpoint Merge branch 'remotes/lorenzo/pci/misc' 2019-05-13 18:34:44 -05:00
hotplug pci-v5.2-changes 2019-05-14 10:30:10 -07:00
pcie pci-v5.2-changes 2019-05-14 10:30:10 -07:00
switch pci-v5.2-changes 2019-05-14 10:30:10 -07:00
access.c PCI: Uninline PCI bus accessors for better ftracing 2018-10-04 16:37:37 -05:00
ats.c PCI/ATS: Add pci_ats_page_aligned() interface 2019-02-26 11:08:07 +01:00
bus.c PCI: Replace dev_printk(KERN_DEBUG) with dev_info(), etc 2019-05-09 07:49:58 -05:00
ecam.c PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate 2018-01-28 15:48:29 -06:00
host-bridge.c PCI: Tidy comments 2018-03-19 14:20:43 -05:00
iov.c PCI/IOV: Add flag so platforms can skip VF scanning 2019-01-01 19:04:37 -06:00
irq.c PCI: Use IRQF_ONESHOT if pci_request_irq() called with no handler 2018-07-31 10:43:43 -05:00
Kconfig PCI: Fix PCI kconfig menu organization 2019-01-14 17:01:20 -06:00
Makefile PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers 2019-04-15 13:24:02 +01:00
mmap.c PCI: Tidy comments 2018-03-19 14:20:43 -05:00
msi.c PCI: Add pci_dev_id() helper 2019-04-29 16:12:05 -05:00
of.c Merge branch 'remotes/lorenzo/pci/keystone' 2019-05-13 18:34:41 -05:00
p2pdma.c PCI/P2PDMA: Allow P2P DMA between any devices under AMD ZEN Root Complex 2019-05-01 16:53:39 -05:00
pci-acpi.c Merge branch 'pci/printk' 2019-05-13 18:34:46 -05:00
pci-bridge-emul.c PCI: pci-bridge-emul: Extend pci_bridge_emul_init() with flags 2019-02-22 10:51:14 +00:00
pci-bridge-emul.h PCI: pci-bridge-emul: Extend pci_bridge_emul_init() with flags 2019-02-22 10:51:14 +00:00
pci-driver.c Printk changes for 5.2 2019-05-07 09:18:12 -07:00
pci-label.c PCI: Tidy comments 2018-03-19 14:20:43 -05:00
pci-mid.c x86/cpu: Sanitize FAM6_ATOM naming 2018-10-02 10:14:32 +02:00
pci-pf-stub.c PCI/IOV: Add pci-pf-stub driver for PFs that only enable VFs 2018-04-24 16:47:16 -05:00
pci-stub.c PCI: Replace printk(KERN_INFO) with pr_info(), etc 2019-05-09 07:49:54 -05:00
pci-sysfs.c PCI: Use dev_printk() when possible 2019-05-09 07:49:49 -05:00
pci.c pci-v5.2-changes 2019-05-14 10:30:10 -07:00
pci.h pci-v5.2-changes 2019-05-14 10:30:10 -07:00
probe.c pci-v5.2-changes 2019-05-14 10:30:10 -07:00
proc.c PCI: Mark expected switch fall-throughs 2019-03-20 15:11:11 -05:00
quirks.c pci-v5.2-changes 2019-05-14 10:30:10 -07:00
remove.c PCI/ASPM: Fix link_state teardown on device removal 2018-09-17 16:32:23 -05:00
rom.c PCI: Make pci_get_rom_size() static 2018-06-29 21:17:26 -05:00
search.c PCI: Add pci_dev_id() helper 2019-04-29 16:12:05 -05:00
setup-bus.c Merge branch 'pci/trivial' 2019-05-13 18:34:48 -05:00
setup-irq.c PCI: Tidy comments 2018-03-19 14:20:43 -05:00
setup-res.c PCI: Remove messages about reassigning resources 2018-04-11 08:46:50 -05:00
slot.c PCI: Replace printk(KERN_INFO) with pr_info(), etc 2019-05-09 07:49:54 -05:00
syscall.c PCI: Tidy comments 2018-03-19 14:20:43 -05:00
vc.c Merge branch 'pci/spdx' into next 2018-02-01 11:40:07 -06:00
vpd.c PCI/VPD: Check for VPD access completion before checking for timeout 2018-08-14 16:04:46 -05:00
xen-pcifront.c Merge branch 'pci/printk' 2019-05-13 18:34:46 -05:00