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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e943da471a
This patch adds a LCD driver supporting the OTM3225A LCD SoC from ORISE Technology. This device can drive TFT LC panels having a resolution of 240x320 pixels. After initializing the OTM3225A using it's SPI interface it switches to use 16-bib RGB as external display interface. Signed-off-by: Felix Brack <fb@ltec.ch> Acked-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
253 lines
7.0 KiB
C
253 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Driver for ORISE Technology OTM3225A SOC for TFT LCD
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* Copyright (C) 2017, EETS GmbH, Felix Brack <fb@ltec.ch>
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*
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* This driver implements a lcd device for the ORISE OTM3225A display
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* controller. The control interface to the display is SPI and the display's
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* memory is updated over the 16-bit RGB interface.
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* The main source of information for writing this driver was provided by the
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* OTM3225A datasheet from ORISE Technology. Some information arise from the
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* ILI9328 datasheet from ILITEK as well as from the datasheets and sample code
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* provided by Crystalfontz America Inc. who sells the CFAF240320A-032T, a 3.2"
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* TFT LC display using the OTM3225A controller.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/lcd.h>
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#include <linux/module.h>
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#include <linux/spi/spi.h>
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#define OTM3225A_INDEX_REG 0x70
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#define OTM3225A_DATA_REG 0x72
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/* instruction register list */
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#define DRIVER_OUTPUT_CTRL_1 0x01
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#define DRIVER_WAVEFORM_CTRL 0x02
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#define ENTRY_MODE 0x03
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#define SCALING_CTRL 0x04
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#define DISPLAY_CTRL_1 0x07
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#define DISPLAY_CTRL_2 0x08
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#define DISPLAY_CTRL_3 0x09
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#define FRAME_CYCLE_CTRL 0x0A
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#define EXT_DISP_IFACE_CTRL_1 0x0C
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#define FRAME_MAKER_POS 0x0D
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#define EXT_DISP_IFACE_CTRL_2 0x0F
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#define POWER_CTRL_1 0x10
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#define POWER_CTRL_2 0x11
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#define POWER_CTRL_3 0x12
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#define POWER_CTRL_4 0x13
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#define GRAM_ADDR_HORIZ_SET 0x20
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#define GRAM_ADDR_VERT_SET 0x21
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#define GRAM_READ_WRITE 0x22
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#define POWER_CTRL_7 0x29
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#define FRAME_RATE_CTRL 0x2B
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#define GAMMA_CTRL_1 0x30
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#define GAMMA_CTRL_2 0x31
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#define GAMMA_CTRL_3 0x32
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#define GAMMA_CTRL_4 0x35
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#define GAMMA_CTRL_5 0x36
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#define GAMMA_CTRL_6 0x37
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#define GAMMA_CTRL_7 0x38
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#define GAMMA_CTRL_8 0x39
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#define GAMMA_CTRL_9 0x3C
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#define GAMMA_CTRL_10 0x3D
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#define WINDOW_HORIZ_RAM_START 0x50
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#define WINDOW_HORIZ_RAM_END 0x51
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#define WINDOW_VERT_RAM_START 0x52
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#define WINDOW_VERT_RAM_END 0x53
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#define DRIVER_OUTPUT_CTRL_2 0x60
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#define BASE_IMG_DISPLAY_CTRL 0x61
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#define VERT_SCROLL_CTRL 0x6A
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#define PD1_DISPLAY_POS 0x80
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#define PD1_RAM_START 0x81
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#define PD1_RAM_END 0x82
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#define PD2_DISPLAY_POS 0x83
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#define PD2_RAM_START 0x84
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#define PD2_RAM_END 0x85
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#define PANEL_IFACE_CTRL_1 0x90
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#define PANEL_IFACE_CTRL_2 0x92
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#define PANEL_IFACE_CTRL_4 0x95
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#define PANEL_IFACE_CTRL_5 0x97
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struct otm3225a_data {
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struct spi_device *spi;
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struct lcd_device *ld;
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int power;
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};
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struct otm3225a_spi_instruction {
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unsigned char reg; /* register to write */
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unsigned short value; /* data to write to 'reg' */
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unsigned short delay; /* delay in ms after write */
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};
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static struct otm3225a_spi_instruction display_init[] = {
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{ DRIVER_OUTPUT_CTRL_1, 0x0000, 0 },
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{ DRIVER_WAVEFORM_CTRL, 0x0700, 0 },
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{ ENTRY_MODE, 0x50A0, 0 },
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{ SCALING_CTRL, 0x0000, 0 },
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{ DISPLAY_CTRL_2, 0x0606, 0 },
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{ DISPLAY_CTRL_3, 0x0000, 0 },
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{ FRAME_CYCLE_CTRL, 0x0000, 0 },
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{ EXT_DISP_IFACE_CTRL_1, 0x0000, 0 },
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{ FRAME_MAKER_POS, 0x0000, 0 },
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{ EXT_DISP_IFACE_CTRL_2, 0x0002, 0 },
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{ POWER_CTRL_2, 0x0007, 0 },
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{ POWER_CTRL_3, 0x0000, 0 },
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{ POWER_CTRL_4, 0x0000, 200 },
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{ DISPLAY_CTRL_1, 0x0101, 0 },
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{ POWER_CTRL_1, 0x12B0, 0 },
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{ POWER_CTRL_2, 0x0007, 0 },
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{ POWER_CTRL_3, 0x01BB, 50 },
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{ POWER_CTRL_4, 0x0013, 0 },
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{ POWER_CTRL_7, 0x0010, 50 },
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{ GAMMA_CTRL_1, 0x000A, 0 },
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{ GAMMA_CTRL_2, 0x1326, 0 },
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{ GAMMA_CTRL_3, 0x0A29, 0 },
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{ GAMMA_CTRL_4, 0x0A0A, 0 },
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{ GAMMA_CTRL_5, 0x1E03, 0 },
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{ GAMMA_CTRL_6, 0x031E, 0 },
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{ GAMMA_CTRL_7, 0x0706, 0 },
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{ GAMMA_CTRL_8, 0x0303, 0 },
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{ GAMMA_CTRL_9, 0x010E, 0 },
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{ GAMMA_CTRL_10, 0x040E, 0 },
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{ WINDOW_HORIZ_RAM_START, 0x0000, 0 },
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{ WINDOW_HORIZ_RAM_END, 0x00EF, 0 },
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{ WINDOW_VERT_RAM_START, 0x0000, 0 },
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{ WINDOW_VERT_RAM_END, 0x013F, 0 },
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{ DRIVER_OUTPUT_CTRL_2, 0x2700, 0 },
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{ BASE_IMG_DISPLAY_CTRL, 0x0001, 0 },
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{ VERT_SCROLL_CTRL, 0x0000, 0 },
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{ PD1_DISPLAY_POS, 0x0000, 0 },
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{ PD1_RAM_START, 0x0000, 0 },
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{ PD1_RAM_END, 0x0000, 0 },
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{ PD2_DISPLAY_POS, 0x0000, 0 },
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{ PD2_RAM_START, 0x0000, 0 },
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{ PD2_RAM_END, 0x0000, 0 },
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{ PANEL_IFACE_CTRL_1, 0x0010, 0 },
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{ PANEL_IFACE_CTRL_2, 0x0000, 0 },
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{ PANEL_IFACE_CTRL_4, 0x0210, 0 },
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{ PANEL_IFACE_CTRL_5, 0x0000, 0 },
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{ DISPLAY_CTRL_1, 0x0133, 0 },
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};
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static struct otm3225a_spi_instruction display_enable_rgb_interface[] = {
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{ ENTRY_MODE, 0x1080, 0 },
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{ GRAM_ADDR_HORIZ_SET, 0x0000, 0 },
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{ GRAM_ADDR_VERT_SET, 0x0000, 0 },
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{ EXT_DISP_IFACE_CTRL_1, 0x0111, 500 },
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};
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static struct otm3225a_spi_instruction display_off[] = {
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{ DISPLAY_CTRL_1, 0x0131, 100 },
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{ DISPLAY_CTRL_1, 0x0130, 100 },
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{ DISPLAY_CTRL_1, 0x0100, 0 },
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{ POWER_CTRL_1, 0x0280, 0 },
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{ POWER_CTRL_3, 0x018B, 0 },
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};
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static struct otm3225a_spi_instruction display_on[] = {
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{ POWER_CTRL_1, 0x1280, 0 },
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{ DISPLAY_CTRL_1, 0x0101, 100 },
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{ DISPLAY_CTRL_1, 0x0121, 0 },
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{ DISPLAY_CTRL_1, 0x0123, 100 },
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{ DISPLAY_CTRL_1, 0x0133, 10 },
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};
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static void otm3225a_write(struct spi_device *spi,
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struct otm3225a_spi_instruction *instruction,
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unsigned int count)
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{
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unsigned char buf[3];
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while (count--) {
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/* address register using index register */
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buf[0] = OTM3225A_INDEX_REG;
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buf[1] = 0x00;
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buf[2] = instruction->reg;
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spi_write(spi, buf, 3);
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/* write data to addressed register */
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buf[0] = OTM3225A_DATA_REG;
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buf[1] = (instruction->value >> 8) & 0xff;
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buf[2] = instruction->value & 0xff;
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spi_write(spi, buf, 3);
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/* execute delay if any */
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if (instruction->delay)
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msleep(instruction->delay);
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instruction++;
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}
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}
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static int otm3225a_set_power(struct lcd_device *ld, int power)
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{
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struct otm3225a_data *dd = lcd_get_data(ld);
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if (power == dd->power)
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return 0;
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if (power > FB_BLANK_UNBLANK)
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otm3225a_write(dd->spi, display_off, ARRAY_SIZE(display_off));
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else
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otm3225a_write(dd->spi, display_on, ARRAY_SIZE(display_on));
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dd->power = power;
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return 0;
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}
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static int otm3225a_get_power(struct lcd_device *ld)
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{
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struct otm3225a_data *dd = lcd_get_data(ld);
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return dd->power;
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}
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static struct lcd_ops otm3225a_ops = {
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.set_power = otm3225a_set_power,
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.get_power = otm3225a_get_power,
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};
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static int otm3225a_probe(struct spi_device *spi)
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{
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struct otm3225a_data *dd;
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struct lcd_device *ld;
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struct device *dev = &spi->dev;
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dd = devm_kzalloc(dev, sizeof(struct otm3225a_data), GFP_KERNEL);
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if (dd == NULL)
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return -ENOMEM;
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ld = devm_lcd_device_register(dev, dev_name(dev), dev, dd,
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&otm3225a_ops);
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if (IS_ERR(ld))
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return PTR_ERR(ld);
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dd->spi = spi;
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dd->ld = ld;
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dev_set_drvdata(dev, dd);
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dev_info(dev, "Initializing and switching to RGB interface");
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otm3225a_write(spi, display_init, ARRAY_SIZE(display_init));
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otm3225a_write(spi, display_enable_rgb_interface,
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ARRAY_SIZE(display_enable_rgb_interface));
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return 0;
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}
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static struct spi_driver otm3225a_driver = {
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.driver = {
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.name = "otm3225a",
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.owner = THIS_MODULE,
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},
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.probe = otm3225a_probe,
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};
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module_spi_driver(otm3225a_driver);
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MODULE_AUTHOR("Felix Brack <fb@ltec.ch>");
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MODULE_DESCRIPTION("OTM3225A TFT LCD driver");
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MODULE_VERSION("1.0.0");
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MODULE_LICENSE("GPL v2");
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