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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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79ad3b5add
The Tegra 2 SoC has 3 EHCI compatible USB controllers. This patch adds the necessary glue to allow the ehci-hcd driver to work on Tegra 2 SoCs. The platform data is used to configure board-specific phy settings and to configure the operating mode, as one of the ports may be used as a otg port. For additional power saving, the driver supports powering down the phy on bus suspend when it is used, for example, to connect an internal device that use an out-of-band remote wakeup mechanism (e.g. a gpio). Signed-off-by: Benoit Goby <benoit@android.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
221 lines
8.6 KiB
C
221 lines
8.6 KiB
C
/*
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* Copyright (c) 2001-2002 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __LINUX_USB_EHCI_DEF_H
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#define __LINUX_USB_EHCI_DEF_H
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/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
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/* Section 2.2 Host Controller Capability Registers */
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struct ehci_caps {
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/* these fields are specified as 8 and 16 bit registers,
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* but some hosts can't perform 8 or 16 bit PCI accesses.
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*/
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u32 hc_capbase;
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#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
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#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
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u32 hcs_params; /* HCSPARAMS - offset 0x4 */
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#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
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#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
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#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
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#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
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#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
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#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
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#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
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u32 hcc_params; /* HCCPARAMS - offset 0x8 */
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/* EHCI 1.1 addendum */
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#define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19))
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#define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18))
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#define HCC_LPM(p) ((p)&(1 << 17))
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#define HCC_HW_PREFETCH(p) ((p)&(1 << 16))
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#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
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#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
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#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
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#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
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#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
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#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
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u8 portroute[8]; /* nibbles for routing - offset 0xC */
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} __attribute__ ((packed));
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/* Section 2.3 Host Controller Operational Registers */
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struct ehci_regs {
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/* USBCMD: offset 0x00 */
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u32 command;
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/* EHCI 1.1 addendum */
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#define CMD_HIRD (0xf<<24) /* host initiated resume duration */
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#define CMD_PPCEE (1<<15) /* per port change event enable */
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#define CMD_FSP (1<<14) /* fully synchronized prefetch */
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#define CMD_ASPE (1<<13) /* async schedule prefetch enable */
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#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */
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/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
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#define CMD_PARK (1<<11) /* enable "park" on async qh */
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#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
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#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
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#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
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#define CMD_ASE (1<<5) /* async schedule enable */
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#define CMD_PSE (1<<4) /* periodic schedule enable */
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/* 3:2 is periodic frame list size */
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#define CMD_RESET (1<<1) /* reset HC not bus */
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#define CMD_RUN (1<<0) /* start/stop HC */
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/* USBSTS: offset 0x04 */
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u32 status;
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#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */
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#define STS_ASS (1<<15) /* Async Schedule Status */
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#define STS_PSS (1<<14) /* Periodic Schedule Status */
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#define STS_RECL (1<<13) /* Reclamation */
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#define STS_HALT (1<<12) /* Not running (any reason) */
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/* some bits reserved */
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/* these STS_* flags are also intr_enable bits (USBINTR) */
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#define STS_IAA (1<<5) /* Interrupted on async advance */
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#define STS_FATAL (1<<4) /* such as some PCI access errors */
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#define STS_FLR (1<<3) /* frame list rolled over */
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#define STS_PCD (1<<2) /* port change detect */
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#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
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#define STS_INT (1<<0) /* "normal" completion (short, ...) */
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/* USBINTR: offset 0x08 */
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u32 intr_enable;
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/* FRINDEX: offset 0x0C */
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u32 frame_index; /* current microframe number */
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/* CTRLDSSEGMENT: offset 0x10 */
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u32 segment; /* address bits 63:32 if needed */
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/* PERIODICLISTBASE: offset 0x14 */
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u32 frame_list; /* points to periodic list */
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/* ASYNCLISTADDR: offset 0x18 */
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u32 async_next; /* address of next async queue head */
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u32 reserved[9];
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/* CONFIGFLAG: offset 0x40 */
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u32 configured_flag;
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#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
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/* PORTSC: offset 0x44 */
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u32 port_status[0]; /* up to N_PORTS */
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/* EHCI 1.1 addendum */
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#define PORTSC_SUSPEND_STS_ACK 0
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#define PORTSC_SUSPEND_STS_NYET 1
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#define PORTSC_SUSPEND_STS_STALL 2
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#define PORTSC_SUSPEND_STS_ERR 3
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#define PORT_DEV_ADDR (0x7f<<25) /* device address */
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#define PORT_SSTS (0x3<<23) /* suspend status */
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/* 31:23 reserved */
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#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
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#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
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#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
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/* 19:16 for port testing */
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#define PORT_TEST(x) (((x)&0xf)<<16) /* Port Test Control */
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#define PORT_TEST_PKT PORT_TEST(0x4) /* Port Test Control - packet test */
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#define PORT_TEST_FORCE PORT_TEST(0x5) /* Port Test Control - force enable */
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#define PORT_LED_OFF (0<<14)
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#define PORT_LED_AMBER (1<<14)
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#define PORT_LED_GREEN (2<<14)
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#define PORT_LED_MASK (3<<14)
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#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
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#define PORT_POWER (1<<12) /* true: has power (see PPC) */
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#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
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/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
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/* 9 reserved */
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#define PORT_LPM (1<<9) /* LPM transaction */
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#define PORT_RESET (1<<8) /* reset port */
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#define PORT_SUSPEND (1<<7) /* suspend port */
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#define PORT_RESUME (1<<6) /* resume it */
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#define PORT_OCC (1<<5) /* over current change */
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#define PORT_OC (1<<4) /* over current active */
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#define PORT_PEC (1<<3) /* port enable change */
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#define PORT_PE (1<<2) /* port enable */
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#define PORT_CSC (1<<1) /* connect status change */
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#define PORT_CONNECT (1<<0) /* device connected */
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#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
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} __attribute__ ((packed));
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#define USBMODE 0x68 /* USB Device mode */
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#define USBMODE_SDIS (1<<3) /* Stream disable */
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#define USBMODE_BE (1<<2) /* BE/LE endianness select */
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#define USBMODE_CM_HC (3<<0) /* host controller mode */
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#define USBMODE_CM_IDLE (0<<0) /* idle state */
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/* Moorestown has some non-standard registers, partially due to the fact that
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* its EHCI controller has both TT and LPM support. HOSTPCx are extentions to
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* PORTSCx
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*/
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#define HOSTPC0 0x84 /* HOSTPC extension */
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#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
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#define HOSTPC_PSPD (3<<25) /* Port speed detection */
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#define USBMODE_EX 0xc8 /* USB Device mode extension */
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#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
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#define USBMODE_EX_HC (3<<0) /* host controller mode */
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#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */
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#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
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/* Appendix C, Debug port ... intended for use with special "debug devices"
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* that can help if there's no serial console. (nonstandard enumeration.)
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*/
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struct ehci_dbg_port {
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u32 control;
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#define DBGP_OWNER (1<<30)
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#define DBGP_ENABLED (1<<28)
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#define DBGP_DONE (1<<16)
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#define DBGP_INUSE (1<<10)
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#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
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# define DBGP_ERR_BAD 1
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# define DBGP_ERR_SIGNAL 2
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#define DBGP_ERROR (1<<6)
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#define DBGP_GO (1<<5)
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#define DBGP_OUT (1<<4)
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#define DBGP_LEN(x) (((x)>>0)&0x0f)
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u32 pids;
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#define DBGP_PID_GET(x) (((x)>>16)&0xff)
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#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
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u32 data03;
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u32 data47;
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u32 address;
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#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
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} __attribute__ ((packed));
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#ifdef CONFIG_EARLY_PRINTK_DBGP
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#include <linux/init.h>
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extern int __init early_dbgp_init(char *s);
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extern struct console early_dbgp_console;
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#endif /* CONFIG_EARLY_PRINTK_DBGP */
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#ifdef CONFIG_EARLY_PRINTK_DBGP
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/* Call backs from ehci host driver to ehci debug driver */
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extern int dbgp_external_startup(void);
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extern int dbgp_reset_prep(void);
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#else
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static inline int dbgp_reset_prep(void)
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{
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return 1;
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}
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static inline int dbgp_external_startup(void)
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{
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return -1;
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}
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#endif
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#endif /* __LINUX_USB_EHCI_DEF_H */
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