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44b12d4311
This patch adds Cortex-A53 CPU{0,1}, Cortex-A53 SCU, Cortex-R7, A3VC,
A2VC1 and 3DG-{A,B} power domain areas for the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[shimoda: fix 3DG-{A,B} and add SPDX-License-Identifier]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
58 lines
1.7 KiB
Plaintext
58 lines
1.7 KiB
Plaintext
DT bindings for the Renesas R-Car (RZ/G) System Controller
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== System Controller Node ==
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The R-Car (RZ/G) System Controller provides power management for the CPU cores
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and various coprocessors.
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Required properties:
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- compatible: Must contain exactly one of the following:
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- "renesas,r8a7743-sysc" (RZ/G1M)
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- "renesas,r8a7745-sysc" (RZ/G1E)
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- "renesas,r8a77470-sysc" (RZ/G1C)
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- "renesas,r8a7779-sysc" (R-Car H1)
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- "renesas,r8a7790-sysc" (R-Car H2)
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- "renesas,r8a7791-sysc" (R-Car M2-W)
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- "renesas,r8a7792-sysc" (R-Car V2H)
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- "renesas,r8a7793-sysc" (R-Car M2-N)
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- "renesas,r8a7794-sysc" (R-Car E2)
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- "renesas,r8a7795-sysc" (R-Car H3)
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- "renesas,r8a7796-sysc" (R-Car M3-W)
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- "renesas,r8a77965-sysc" (R-Car M3-N)
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- "renesas,r8a77970-sysc" (R-Car V3M)
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- "renesas,r8a77980-sysc" (R-Car V3H)
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- "renesas,r8a77990-sysc" (R-Car E3)
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- "renesas,r8a77995-sysc" (R-Car D3)
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- reg: Address start and address range for the device.
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- #power-domain-cells: Must be 1.
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Example:
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7791-sysc";
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reg = <0 0xe6180000 0 0x0200>;
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#power-domain-cells = <1>;
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};
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== PM Domain Consumers ==
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Devices residing in a power area must refer to that power area, as documented
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by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Required properties:
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- power-domains: A phandle and symbolic PM domain specifier, as defined in
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<dt-bindings/power/r8a77*-sysc.h>.
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Example:
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L2_CA15: cache-controller@0 {
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compatible = "cache";
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power-domains = <&sysc R8A7791_PD_CA15_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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