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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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17d48610ae
This patch implements P(Presented)/Q(Queued) states for ICS irqs. When the interrupt is presented, set P. Present if P was not set. If P is already set, don't present again, set Q. When the interrupt is EOI'ed, move Q into P (and clear Q). If it is set, re-present. The asserted flag used by LSI is also incorporated into the P bit. When the irq state is saved, P/Q bits are also saved, they need some qemu modifications to be recognized and passed around to be restored. KVM_XICS_PENDING bit set and saved should also indicate KVM_XICS_PRESENTED bit set and saved. But it is possible some old code doesn't have/recognize the P bit, so when we restore, we set P for PENDING bit, too. The idea and much of the code come from Ben. Signed-off-by: Li Zhong <zhong@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
925 lines
24 KiB
C
925 lines
24 KiB
C
/*
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* Copyright 2012 Michael Ellerman, IBM Corporation.
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* Copyright 2012 Benjamin Herrenschmidt, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/kvm_host.h>
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#include <linux/err.h>
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#include <linux/kernel_stat.h>
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#include <asm/kvm_book3s.h>
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#include <asm/kvm_ppc.h>
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#include <asm/hvcall.h>
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#include <asm/xics.h>
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#include <asm/debug.h>
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#include <asm/synch.h>
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#include <asm/cputhreads.h>
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#include <asm/pgtable.h>
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#include <asm/ppc-opcode.h>
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#include <asm/pnv-pci.h>
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#include <asm/opal.h>
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#include <asm/smp.h>
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#include "book3s_xics.h"
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#define DEBUG_PASSUP
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int h_ipi_redirect = 1;
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EXPORT_SYMBOL(h_ipi_redirect);
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int kvm_irq_bypass = 1;
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EXPORT_SYMBOL(kvm_irq_bypass);
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static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u32 new_irq);
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static int xics_opal_rm_set_server(unsigned int hw_irq, int server_cpu);
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/* -- ICS routines -- */
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static void ics_rm_check_resend(struct kvmppc_xics *xics,
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struct kvmppc_ics *ics, struct kvmppc_icp *icp)
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{
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int i;
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arch_spin_lock(&ics->lock);
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for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
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struct ics_irq_state *state = &ics->irq_state[i];
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if (!state->resend)
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continue;
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state->resend = 0;
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arch_spin_unlock(&ics->lock);
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icp_rm_deliver_irq(xics, icp, state->number);
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arch_spin_lock(&ics->lock);
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}
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arch_spin_unlock(&ics->lock);
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}
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/* -- ICP routines -- */
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#ifdef CONFIG_SMP
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static inline void icp_send_hcore_msg(int hcore, struct kvm_vcpu *vcpu)
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{
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int hcpu;
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hcpu = hcore << threads_shift;
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kvmppc_host_rm_ops_hv->rm_core[hcore].rm_data = vcpu;
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smp_muxed_ipi_set_message(hcpu, PPC_MSG_RM_HOST_ACTION);
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if (paca[hcpu].kvm_hstate.xics_phys)
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icp_native_cause_ipi_rm(hcpu);
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else
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opal_rm_int_set_mfrr(get_hard_smp_processor_id(hcpu),
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IPI_PRIORITY);
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}
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#else
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static inline void icp_send_hcore_msg(int hcore, struct kvm_vcpu *vcpu) { }
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#endif
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/*
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* We start the search from our current CPU Id in the core map
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* and go in a circle until we get back to our ID looking for a
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* core that is running in host context and that hasn't already
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* been targeted for another rm_host_ops.
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*
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* In the future, could consider using a fairer algorithm (one
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* that distributes the IPIs better)
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*
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* Returns -1, if no CPU could be found in the host
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* Else, returns a CPU Id which has been reserved for use
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*/
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static inline int grab_next_hostcore(int start,
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struct kvmppc_host_rm_core *rm_core, int max, int action)
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{
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bool success;
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int core;
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union kvmppc_rm_state old, new;
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for (core = start + 1; core < max; core++) {
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old = new = READ_ONCE(rm_core[core].rm_state);
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if (!old.in_host || old.rm_action)
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continue;
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/* Try to grab this host core if not taken already. */
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new.rm_action = action;
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success = cmpxchg64(&rm_core[core].rm_state.raw,
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old.raw, new.raw) == old.raw;
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if (success) {
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/*
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* Make sure that the store to the rm_action is made
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* visible before we return to caller (and the
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* subsequent store to rm_data) to synchronize with
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* the IPI handler.
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*/
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smp_wmb();
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return core;
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}
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}
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return -1;
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}
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static inline int find_available_hostcore(int action)
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{
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int core;
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int my_core = smp_processor_id() >> threads_shift;
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struct kvmppc_host_rm_core *rm_core = kvmppc_host_rm_ops_hv->rm_core;
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core = grab_next_hostcore(my_core, rm_core, cpu_nr_cores(), action);
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if (core == -1)
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core = grab_next_hostcore(core, rm_core, my_core, action);
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return core;
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}
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static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu,
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struct kvm_vcpu *this_vcpu)
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{
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struct kvmppc_icp *this_icp = this_vcpu->arch.icp;
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int cpu;
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int hcore;
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/* Mark the target VCPU as having an interrupt pending */
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vcpu->stat.queue_intr++;
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set_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
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/* Kick self ? Just set MER and return */
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if (vcpu == this_vcpu) {
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_MER);
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return;
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}
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/*
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* Check if the core is loaded,
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* if not, find an available host core to post to wake the VCPU,
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* if we can't find one, set up state to eventually return too hard.
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*/
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cpu = vcpu->arch.thread_cpu;
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if (cpu < 0 || cpu >= nr_cpu_ids) {
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hcore = -1;
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if (kvmppc_host_rm_ops_hv && h_ipi_redirect)
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hcore = find_available_hostcore(XICS_RM_KICK_VCPU);
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if (hcore != -1) {
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icp_send_hcore_msg(hcore, vcpu);
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} else {
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this_icp->rm_action |= XICS_RM_KICK_VCPU;
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this_icp->rm_kick_target = vcpu;
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}
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return;
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}
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smp_mb();
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kvmhv_rm_send_ipi(cpu);
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}
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static void icp_rm_clr_vcpu_irq(struct kvm_vcpu *vcpu)
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{
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/* Note: Only called on self ! */
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clear_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL,
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&vcpu->arch.pending_exceptions);
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_MER);
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}
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static inline bool icp_rm_try_update(struct kvmppc_icp *icp,
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union kvmppc_icp_state old,
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union kvmppc_icp_state new)
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{
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struct kvm_vcpu *this_vcpu = local_paca->kvm_hstate.kvm_vcpu;
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bool success;
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/* Calculate new output value */
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new.out_ee = (new.xisr && (new.pending_pri < new.cppr));
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/* Attempt atomic update */
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success = cmpxchg64(&icp->state.raw, old.raw, new.raw) == old.raw;
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if (!success)
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goto bail;
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/*
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* Check for output state update
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*
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* Note that this is racy since another processor could be updating
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* the state already. This is why we never clear the interrupt output
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* here, we only ever set it. The clear only happens prior to doing
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* an update and only by the processor itself. Currently we do it
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* in Accept (H_XIRR) and Up_Cppr (H_XPPR).
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*
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* We also do not try to figure out whether the EE state has changed,
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* we unconditionally set it if the new state calls for it. The reason
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* for that is that we opportunistically remove the pending interrupt
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* flag when raising CPPR, so we need to set it back here if an
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* interrupt is still pending.
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*/
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if (new.out_ee)
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icp_rm_set_vcpu_irq(icp->vcpu, this_vcpu);
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/* Expose the state change for debug purposes */
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this_vcpu->arch.icp->rm_dbgstate = new;
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this_vcpu->arch.icp->rm_dbgtgt = icp->vcpu;
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bail:
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return success;
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}
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static inline int check_too_hard(struct kvmppc_xics *xics,
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struct kvmppc_icp *icp)
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{
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return (xics->real_mode_dbg || icp->rm_action) ? H_TOO_HARD : H_SUCCESS;
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}
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static void icp_rm_check_resend(struct kvmppc_xics *xics,
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struct kvmppc_icp *icp)
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{
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u32 icsid;
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/* Order this load with the test for need_resend in the caller */
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smp_rmb();
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for_each_set_bit(icsid, icp->resend_map, xics->max_icsid + 1) {
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struct kvmppc_ics *ics = xics->ics[icsid];
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if (!test_and_clear_bit(icsid, icp->resend_map))
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continue;
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if (!ics)
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continue;
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ics_rm_check_resend(xics, ics, icp);
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}
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}
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static bool icp_rm_try_to_deliver(struct kvmppc_icp *icp, u32 irq, u8 priority,
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u32 *reject)
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{
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union kvmppc_icp_state old_state, new_state;
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bool success;
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do {
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old_state = new_state = READ_ONCE(icp->state);
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*reject = 0;
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/* See if we can deliver */
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success = new_state.cppr > priority &&
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new_state.mfrr > priority &&
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new_state.pending_pri > priority;
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/*
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* If we can, check for a rejection and perform the
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* delivery
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*/
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if (success) {
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*reject = new_state.xisr;
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new_state.xisr = irq;
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new_state.pending_pri = priority;
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} else {
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/*
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* If we failed to deliver we set need_resend
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* so a subsequent CPPR state change causes us
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* to try a new delivery.
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*/
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new_state.need_resend = true;
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}
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} while (!icp_rm_try_update(icp, old_state, new_state));
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return success;
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}
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static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u32 new_irq)
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{
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struct ics_irq_state *state;
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struct kvmppc_ics *ics;
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u32 reject;
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u16 src;
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/*
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* This is used both for initial delivery of an interrupt and
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* for subsequent rejection.
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*
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* Rejection can be racy vs. resends. We have evaluated the
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* rejection in an atomic ICP transaction which is now complete,
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* so potentially the ICP can already accept the interrupt again.
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*
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* So we need to retry the delivery. Essentially the reject path
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* boils down to a failed delivery. Always.
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*
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* Now the interrupt could also have moved to a different target,
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* thus we may need to re-do the ICP lookup as well
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*/
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again:
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/* Get the ICS state and lock it */
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ics = kvmppc_xics_find_ics(xics, new_irq, &src);
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if (!ics) {
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/* Unsafe increment, but this does not need to be accurate */
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xics->err_noics++;
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return;
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}
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state = &ics->irq_state[src];
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/* Get a lock on the ICS */
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arch_spin_lock(&ics->lock);
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/* Get our server */
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if (!icp || state->server != icp->server_num) {
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icp = kvmppc_xics_find_server(xics->kvm, state->server);
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if (!icp) {
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/* Unsafe increment again*/
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xics->err_noicp++;
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goto out;
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}
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}
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/* Clear the resend bit of that interrupt */
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state->resend = 0;
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/*
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* If masked, bail out
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*
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* Note: PAPR doesn't mention anything about masked pending
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* when doing a resend, only when doing a delivery.
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*
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* However that would have the effect of losing a masked
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* interrupt that was rejected and isn't consistent with
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* the whole masked_pending business which is about not
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* losing interrupts that occur while masked.
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*
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* I don't differentiate normal deliveries and resends, this
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* implementation will differ from PAPR and not lose such
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* interrupts.
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*/
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if (state->priority == MASKED) {
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state->masked_pending = 1;
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goto out;
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}
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/*
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* Try the delivery, this will set the need_resend flag
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* in the ICP as part of the atomic transaction if the
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* delivery is not possible.
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*
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* Note that if successful, the new delivery might have itself
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* rejected an interrupt that was "delivered" before we took the
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* ics spin lock.
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*
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* In this case we do the whole sequence all over again for the
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* new guy. We cannot assume that the rejected interrupt is less
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* favored than the new one, and thus doesn't need to be delivered,
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* because by the time we exit icp_rm_try_to_deliver() the target
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* processor may well have already consumed & completed it, and thus
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* the rejected interrupt might actually be already acceptable.
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*/
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if (icp_rm_try_to_deliver(icp, new_irq, state->priority, &reject)) {
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/*
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* Delivery was successful, did we reject somebody else ?
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*/
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if (reject && reject != XICS_IPI) {
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arch_spin_unlock(&ics->lock);
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icp->n_reject++;
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new_irq = reject;
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goto again;
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}
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} else {
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/*
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* We failed to deliver the interrupt we need to set the
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* resend map bit and mark the ICS state as needing a resend
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*/
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set_bit(ics->icsid, icp->resend_map);
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state->resend = 1;
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/*
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* If the need_resend flag got cleared in the ICP some time
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* between icp_rm_try_to_deliver() atomic update and now, then
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* we know it might have missed the resend_map bit. So we
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* retry
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*/
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smp_mb();
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if (!icp->state.need_resend) {
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state->resend = 0;
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arch_spin_unlock(&ics->lock);
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goto again;
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}
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}
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out:
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arch_spin_unlock(&ics->lock);
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}
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static void icp_rm_down_cppr(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u8 new_cppr)
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{
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union kvmppc_icp_state old_state, new_state;
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bool resend;
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/*
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* This handles several related states in one operation:
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*
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* ICP State: Down_CPPR
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*
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* Load CPPR with new value and if the XISR is 0
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* then check for resends:
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*
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* ICP State: Resend
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*
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* If MFRR is more favored than CPPR, check for IPIs
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* and notify ICS of a potential resend. This is done
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* asynchronously (when used in real mode, we will have
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* to exit here).
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*
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* We do not handle the complete Check_IPI as documented
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* here. In the PAPR, this state will be used for both
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* Set_MFRR and Down_CPPR. However, we know that we aren't
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* changing the MFRR state here so we don't need to handle
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* the case of an MFRR causing a reject of a pending irq,
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* this will have been handled when the MFRR was set in the
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* first place.
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*
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* Thus we don't have to handle rejects, only resends.
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*
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* When implementing real mode for HV KVM, resend will lead to
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* a H_TOO_HARD return and the whole transaction will be handled
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* in virtual mode.
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*/
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do {
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old_state = new_state = READ_ONCE(icp->state);
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/* Down_CPPR */
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new_state.cppr = new_cppr;
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/*
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* Cut down Resend / Check_IPI / IPI
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*
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* The logic is that we cannot have a pending interrupt
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* trumped by an IPI at this point (see above), so we
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* know that either the pending interrupt is already an
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* IPI (in which case we don't care to override it) or
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* it's either more favored than us or non existent
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*/
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if (new_state.mfrr < new_cppr &&
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new_state.mfrr <= new_state.pending_pri) {
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new_state.pending_pri = new_state.mfrr;
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new_state.xisr = XICS_IPI;
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}
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/* Latch/clear resend bit */
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resend = new_state.need_resend;
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new_state.need_resend = 0;
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} while (!icp_rm_try_update(icp, old_state, new_state));
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/*
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* Now handle resend checks. Those are asynchronous to the ICP
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* state update in HW (ie bus transactions) so we can handle them
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* separately here as well.
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*/
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if (resend) {
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icp->n_check_resend++;
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icp_rm_check_resend(xics, icp);
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}
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}
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unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
u32 xirr;
|
|
|
|
if (!xics || !xics->real_mode)
|
|
return H_TOO_HARD;
|
|
|
|
/* First clear the interrupt */
|
|
icp_rm_clr_vcpu_irq(icp->vcpu);
|
|
|
|
/*
|
|
* ICP State: Accept_Interrupt
|
|
*
|
|
* Return the pending interrupt (if any) along with the
|
|
* current CPPR, then clear the XISR & set CPPR to the
|
|
* pending priority
|
|
*/
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
xirr = old_state.xisr | (((u32)old_state.cppr) << 24);
|
|
if (!old_state.xisr)
|
|
break;
|
|
new_state.cppr = new_state.pending_pri;
|
|
new_state.pending_pri = 0xff;
|
|
new_state.xisr = 0;
|
|
|
|
} while (!icp_rm_try_update(icp, old_state, new_state));
|
|
|
|
/* Return the result in GPR4 */
|
|
vcpu->arch.gpr[4] = xirr;
|
|
|
|
return check_too_hard(xics, icp);
|
|
}
|
|
|
|
int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
|
|
unsigned long mfrr)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp, *this_icp = vcpu->arch.icp;
|
|
u32 reject;
|
|
bool resend;
|
|
bool local;
|
|
|
|
if (!xics || !xics->real_mode)
|
|
return H_TOO_HARD;
|
|
|
|
local = this_icp->server_num == server;
|
|
if (local)
|
|
icp = this_icp;
|
|
else
|
|
icp = kvmppc_xics_find_server(vcpu->kvm, server);
|
|
if (!icp)
|
|
return H_PARAMETER;
|
|
|
|
/*
|
|
* ICP state: Set_MFRR
|
|
*
|
|
* If the CPPR is more favored than the new MFRR, then
|
|
* nothing needs to be done as there can be no XISR to
|
|
* reject.
|
|
*
|
|
* ICP state: Check_IPI
|
|
*
|
|
* If the CPPR is less favored, then we might be replacing
|
|
* an interrupt, and thus need to possibly reject it.
|
|
*
|
|
* ICP State: IPI
|
|
*
|
|
* Besides rejecting any pending interrupts, we also
|
|
* update XISR and pending_pri to mark IPI as pending.
|
|
*
|
|
* PAPR does not describe this state, but if the MFRR is being
|
|
* made less favored than its earlier value, there might be
|
|
* a previously-rejected interrupt needing to be resent.
|
|
* Ideally, we would want to resend only if
|
|
* prio(pending_interrupt) < mfrr &&
|
|
* prio(pending_interrupt) < cppr
|
|
* where pending interrupt is the one that was rejected. But
|
|
* we don't have that state, so we simply trigger a resend
|
|
* whenever the MFRR is made less favored.
|
|
*/
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
/* Set_MFRR */
|
|
new_state.mfrr = mfrr;
|
|
|
|
/* Check_IPI */
|
|
reject = 0;
|
|
resend = false;
|
|
if (mfrr < new_state.cppr) {
|
|
/* Reject a pending interrupt if not an IPI */
|
|
if (mfrr <= new_state.pending_pri) {
|
|
reject = new_state.xisr;
|
|
new_state.pending_pri = mfrr;
|
|
new_state.xisr = XICS_IPI;
|
|
}
|
|
}
|
|
|
|
if (mfrr > old_state.mfrr) {
|
|
resend = new_state.need_resend;
|
|
new_state.need_resend = 0;
|
|
}
|
|
} while (!icp_rm_try_update(icp, old_state, new_state));
|
|
|
|
/* Handle reject in real mode */
|
|
if (reject && reject != XICS_IPI) {
|
|
this_icp->n_reject++;
|
|
icp_rm_deliver_irq(xics, icp, reject);
|
|
}
|
|
|
|
/* Handle resends in real mode */
|
|
if (resend) {
|
|
this_icp->n_check_resend++;
|
|
icp_rm_check_resend(xics, icp);
|
|
}
|
|
|
|
return check_too_hard(xics, this_icp);
|
|
}
|
|
|
|
int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
u32 reject;
|
|
|
|
if (!xics || !xics->real_mode)
|
|
return H_TOO_HARD;
|
|
|
|
/*
|
|
* ICP State: Set_CPPR
|
|
*
|
|
* We can safely compare the new value with the current
|
|
* value outside of the transaction as the CPPR is only
|
|
* ever changed by the processor on itself
|
|
*/
|
|
if (cppr > icp->state.cppr) {
|
|
icp_rm_down_cppr(xics, icp, cppr);
|
|
goto bail;
|
|
} else if (cppr == icp->state.cppr)
|
|
return H_SUCCESS;
|
|
|
|
/*
|
|
* ICP State: Up_CPPR
|
|
*
|
|
* The processor is raising its priority, this can result
|
|
* in a rejection of a pending interrupt:
|
|
*
|
|
* ICP State: Reject_Current
|
|
*
|
|
* We can remove EE from the current processor, the update
|
|
* transaction will set it again if needed
|
|
*/
|
|
icp_rm_clr_vcpu_irq(icp->vcpu);
|
|
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
reject = 0;
|
|
new_state.cppr = cppr;
|
|
|
|
if (cppr <= new_state.pending_pri) {
|
|
reject = new_state.xisr;
|
|
new_state.xisr = 0;
|
|
new_state.pending_pri = 0xff;
|
|
}
|
|
|
|
} while (!icp_rm_try_update(icp, old_state, new_state));
|
|
|
|
/*
|
|
* Check for rejects. They are handled by doing a new delivery
|
|
* attempt (see comments in icp_rm_deliver_irq).
|
|
*/
|
|
if (reject && reject != XICS_IPI) {
|
|
icp->n_reject++;
|
|
icp_rm_deliver_irq(xics, icp, reject);
|
|
}
|
|
bail:
|
|
return check_too_hard(xics, icp);
|
|
}
|
|
|
|
static int ics_rm_eoi(struct kvm_vcpu *vcpu, u32 irq)
|
|
{
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
struct kvmppc_ics *ics;
|
|
struct ics_irq_state *state;
|
|
u16 src;
|
|
u32 pq_old, pq_new;
|
|
|
|
/*
|
|
* ICS EOI handling: For LSI, if P bit is still set, we need to
|
|
* resend it.
|
|
*
|
|
* For MSI, we move Q bit into P (and clear Q). If it is set,
|
|
* resend it.
|
|
*/
|
|
|
|
ics = kvmppc_xics_find_ics(xics, irq, &src);
|
|
if (!ics)
|
|
goto bail;
|
|
|
|
state = &ics->irq_state[src];
|
|
|
|
if (state->lsi)
|
|
pq_new = state->pq_state;
|
|
else
|
|
do {
|
|
pq_old = state->pq_state;
|
|
pq_new = pq_old >> 1;
|
|
} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
|
|
|
|
if (pq_new & PQ_PRESENTED)
|
|
icp_rm_deliver_irq(xics, NULL, irq);
|
|
|
|
if (!hlist_empty(&vcpu->kvm->irq_ack_notifier_list)) {
|
|
icp->rm_action |= XICS_RM_NOTIFY_EOI;
|
|
icp->rm_eoied_irq = irq;
|
|
}
|
|
|
|
if (state->host_irq) {
|
|
++vcpu->stat.pthru_all;
|
|
if (state->intr_cpu != -1) {
|
|
int pcpu = raw_smp_processor_id();
|
|
|
|
pcpu = cpu_first_thread_sibling(pcpu);
|
|
++vcpu->stat.pthru_host;
|
|
if (state->intr_cpu != pcpu) {
|
|
++vcpu->stat.pthru_bad_aff;
|
|
xics_opal_rm_set_server(state->host_irq, pcpu);
|
|
}
|
|
state->intr_cpu = -1;
|
|
}
|
|
}
|
|
|
|
bail:
|
|
return check_too_hard(xics, icp);
|
|
}
|
|
|
|
int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
|
|
{
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
u32 irq = xirr & 0x00ffffff;
|
|
|
|
if (!xics || !xics->real_mode)
|
|
return H_TOO_HARD;
|
|
|
|
/*
|
|
* ICP State: EOI
|
|
*
|
|
* Note: If EOI is incorrectly used by SW to lower the CPPR
|
|
* value (ie more favored), we do not check for rejection of
|
|
* a pending interrupt, this is a SW error and PAPR specifies
|
|
* that we don't have to deal with it.
|
|
*
|
|
* The sending of an EOI to the ICS is handled after the
|
|
* CPPR update
|
|
*
|
|
* ICP State: Down_CPPR which we handle
|
|
* in a separate function as it's shared with H_CPPR.
|
|
*/
|
|
icp_rm_down_cppr(xics, icp, xirr >> 24);
|
|
|
|
/* IPIs have no EOI */
|
|
if (irq == XICS_IPI)
|
|
return check_too_hard(xics, icp);
|
|
|
|
return ics_rm_eoi(vcpu, irq);
|
|
}
|
|
|
|
unsigned long eoi_rc;
|
|
|
|
static void icp_eoi(struct irq_chip *c, u32 hwirq, __be32 xirr, bool *again)
|
|
{
|
|
unsigned long xics_phys;
|
|
int64_t rc;
|
|
|
|
rc = pnv_opal_pci_msi_eoi(c, hwirq);
|
|
|
|
if (rc)
|
|
eoi_rc = rc;
|
|
|
|
iosync();
|
|
|
|
/* EOI it */
|
|
xics_phys = local_paca->kvm_hstate.xics_phys;
|
|
if (xics_phys) {
|
|
_stwcix(xics_phys + XICS_XIRR, xirr);
|
|
} else {
|
|
rc = opal_rm_int_eoi(be32_to_cpu(xirr));
|
|
*again = rc > 0;
|
|
}
|
|
}
|
|
|
|
static int xics_opal_rm_set_server(unsigned int hw_irq, int server_cpu)
|
|
{
|
|
unsigned int mangle_cpu = get_hard_smp_processor_id(server_cpu) << 2;
|
|
|
|
return opal_rm_set_xive(hw_irq, mangle_cpu, DEFAULT_PRIORITY);
|
|
}
|
|
|
|
/*
|
|
* Increment a per-CPU 32-bit unsigned integer variable.
|
|
* Safe to call in real-mode. Handles vmalloc'ed addresses
|
|
*
|
|
* ToDo: Make this work for any integral type
|
|
*/
|
|
|
|
static inline void this_cpu_inc_rm(unsigned int __percpu *addr)
|
|
{
|
|
unsigned long l;
|
|
unsigned int *raddr;
|
|
int cpu = smp_processor_id();
|
|
|
|
raddr = per_cpu_ptr(addr, cpu);
|
|
l = (unsigned long)raddr;
|
|
|
|
if (REGION_ID(l) == VMALLOC_REGION_ID) {
|
|
l = vmalloc_to_phys(raddr);
|
|
raddr = (unsigned int *)l;
|
|
}
|
|
++*raddr;
|
|
}
|
|
|
|
/*
|
|
* We don't try to update the flags in the irq_desc 'istate' field in
|
|
* here as would happen in the normal IRQ handling path for several reasons:
|
|
* - state flags represent internal IRQ state and are not expected to be
|
|
* updated outside the IRQ subsystem
|
|
* - more importantly, these are useful for edge triggered interrupts,
|
|
* IRQ probing, etc., but we are only handling MSI/MSIx interrupts here
|
|
* and these states shouldn't apply to us.
|
|
*
|
|
* However, we do update irq_stats - we somewhat duplicate the code in
|
|
* kstat_incr_irqs_this_cpu() for this since this function is defined
|
|
* in irq/internal.h which we don't want to include here.
|
|
* The only difference is that desc->kstat_irqs is an allocated per CPU
|
|
* variable and could have been vmalloc'ed, so we can't directly
|
|
* call __this_cpu_inc() on it. The kstat structure is a static
|
|
* per CPU variable and it should be accessible by real-mode KVM.
|
|
*
|
|
*/
|
|
static void kvmppc_rm_handle_irq_desc(struct irq_desc *desc)
|
|
{
|
|
this_cpu_inc_rm(desc->kstat_irqs);
|
|
__this_cpu_inc(kstat.irqs_sum);
|
|
}
|
|
|
|
long kvmppc_deliver_irq_passthru(struct kvm_vcpu *vcpu,
|
|
__be32 xirr,
|
|
struct kvmppc_irq_map *irq_map,
|
|
struct kvmppc_passthru_irqmap *pimap,
|
|
bool *again)
|
|
{
|
|
struct kvmppc_xics *xics;
|
|
struct kvmppc_icp *icp;
|
|
struct kvmppc_ics *ics;
|
|
struct ics_irq_state *state;
|
|
u32 irq;
|
|
u16 src;
|
|
u32 pq_old, pq_new;
|
|
|
|
irq = irq_map->v_hwirq;
|
|
xics = vcpu->kvm->arch.xics;
|
|
icp = vcpu->arch.icp;
|
|
|
|
kvmppc_rm_handle_irq_desc(irq_map->desc);
|
|
|
|
ics = kvmppc_xics_find_ics(xics, irq, &src);
|
|
if (!ics)
|
|
return 2;
|
|
|
|
state = &ics->irq_state[src];
|
|
|
|
/* only MSIs register bypass producers, so it must be MSI here */
|
|
do {
|
|
pq_old = state->pq_state;
|
|
pq_new = ((pq_old << 1) & 3) | PQ_PRESENTED;
|
|
} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
|
|
|
|
/* Test P=1, Q=0, this is the only case where we present */
|
|
if (pq_new == PQ_PRESENTED)
|
|
icp_rm_deliver_irq(xics, icp, irq);
|
|
|
|
/* EOI the interrupt */
|
|
icp_eoi(irq_desc_get_chip(irq_map->desc), irq_map->r_hwirq, xirr,
|
|
again);
|
|
|
|
if (check_too_hard(xics, icp) == H_TOO_HARD)
|
|
return 2;
|
|
else
|
|
return -2;
|
|
}
|
|
|
|
/* --- Non-real mode XICS-related built-in routines --- */
|
|
|
|
/**
|
|
* Host Operations poked by RM KVM
|
|
*/
|
|
static void rm_host_ipi_action(int action, void *data)
|
|
{
|
|
switch (action) {
|
|
case XICS_RM_KICK_VCPU:
|
|
kvmppc_host_rm_ops_hv->vcpu_kick(data);
|
|
break;
|
|
default:
|
|
WARN(1, "Unexpected rm_action=%d data=%p\n", action, data);
|
|
break;
|
|
}
|
|
|
|
}
|
|
|
|
void kvmppc_xics_ipi_action(void)
|
|
{
|
|
int core;
|
|
unsigned int cpu = smp_processor_id();
|
|
struct kvmppc_host_rm_core *rm_corep;
|
|
|
|
core = cpu >> threads_shift;
|
|
rm_corep = &kvmppc_host_rm_ops_hv->rm_core[core];
|
|
|
|
if (rm_corep->rm_data) {
|
|
rm_host_ipi_action(rm_corep->rm_state.rm_action,
|
|
rm_corep->rm_data);
|
|
/* Order these stores against the real mode KVM */
|
|
rm_corep->rm_data = NULL;
|
|
smp_wmb();
|
|
rm_corep->rm_state.rm_action = 0;
|
|
}
|
|
}
|