mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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acbde1db29
The existing code relied on the hardware definition (<arch/chip.h>) to specify how much VA and PA space was available. It's convenient to allow customizing this for some configurations, so provide symbols MAX_PA_WIDTH and MAX_VA_WIDTH in <asm/page.h> that can be modified if desired. Additionally, move away from the MEM_XX_INTRPT nomenclature to define the start of various regions within the VA space. In fact the cleaner symbol is, for example, MEM_SV_START, to indicate the start of the area used for supervisor code; the actual address of the interrupt vectors is not as important, and can be changed if desired. As part of this change, convert from "intrpt1" nomenclature (which built in the old privilege-level 1 model) to a simple "intrpt". Also strip out some tilepro-specific code supporting modifying the PL the kernel could run at, since we don't actually support using different PLs in tilepro, only tilegx. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
280 lines
7.3 KiB
ArmAsm
280 lines
7.3 KiB
ArmAsm
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* TILE startup code.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/thread_info.h>
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#include <asm/processor.h>
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#include <asm/asm-offsets.h>
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#include <hv/hypervisor.h>
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#include <arch/chip.h>
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#include <arch/spr_def.h>
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/* Extract two 32-bit bit values that were read into one register. */
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#ifdef __BIG_ENDIAN__
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#define GET_FIRST_INT(rd, rs) shrsi rd, rs, 32
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#define GET_SECOND_INT(rd, rs) addxi rd, rs, 0
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#else
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#define GET_FIRST_INT(rd, rs) addxi rd, rs, 0
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#define GET_SECOND_INT(rd, rs) shrsi rd, rs, 32
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#endif
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/*
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* This module contains the entry code for kernel images. It performs the
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* minimal setup needed to call the generic C routines.
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*/
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__HEAD
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ENTRY(_start)
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/* Notify the hypervisor of what version of the API we want */
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{
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#if KERNEL_PL == 1 && _HV_VERSION == 13
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/* Support older hypervisors by asking for API version 12. */
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movei r0, _HV_VERSION_OLD_HV_INIT
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#else
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movei r0, _HV_VERSION
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#endif
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movei r1, TILE_CHIP
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}
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{
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movei r2, TILE_CHIP_REV
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movei r3, KERNEL_PL
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}
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jal _hv_init
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/* Get a reasonable default ASID in r0 */
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{
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move r0, zero
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jal _hv_inquire_asid
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}
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/*
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* Install the default page table. The relocation required to
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* statically define the table is a bit too complex, so we have
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* to plug in the pointer from the L0 to the L1 table by hand.
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* We only do this on the first cpu to boot, though, since the
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* other CPUs should see a properly-constructed page table.
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*/
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{
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GET_FIRST_INT(r2, r0) /* ASID for hv_install_context */
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moveli r4, hw1_last(swapper_pgprot - PAGE_OFFSET)
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}
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{
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shl16insli r4, r4, hw0(swapper_pgprot - PAGE_OFFSET)
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}
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{
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ld r1, r4 /* access_pte for hv_install_context */
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}
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{
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moveli r0, hw1_last(.Lsv_data_pmd - PAGE_OFFSET)
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moveli r6, hw1_last(temp_data_pmd - PAGE_OFFSET)
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}
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{
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/* After initializing swapper_pgprot, HV_PTE_GLOBAL is set. */
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bfextu r7, r1, HV_PTE_INDEX_GLOBAL, HV_PTE_INDEX_GLOBAL
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finv r4
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}
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bnez r7, .Lno_write
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{
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shl16insli r0, r0, hw0(.Lsv_data_pmd - PAGE_OFFSET)
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shl16insli r6, r6, hw0(temp_data_pmd - PAGE_OFFSET)
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}
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{
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/* Cut off the low bits of the PT address. */
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shrui r6, r6, HV_LOG2_PAGE_TABLE_ALIGN
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/* Start with our access pte. */
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move r5, r1
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}
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{
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/* Stuff the address into the page table pointer slot of the PTE. */
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bfins r5, r6, HV_PTE_INDEX_PTFN, \
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HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
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}
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{
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/* Store the L0 data PTE. */
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st r0, r5
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addli r6, r6, (temp_code_pmd - temp_data_pmd) >> \
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HV_LOG2_PAGE_TABLE_ALIGN
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}
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{
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addli r0, r0, .Lsv_code_pmd - .Lsv_data_pmd
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bfins r5, r6, HV_PTE_INDEX_PTFN, \
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HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
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}
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/* Store the L0 code PTE. */
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st r0, r5
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.Lno_write:
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moveli lr, hw2_last(1f)
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{
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shl16insli lr, lr, hw1(1f)
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moveli r0, hw1_last(swapper_pg_dir - PAGE_OFFSET)
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}
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{
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shl16insli lr, lr, hw0(1f)
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shl16insli r0, r0, hw0(swapper_pg_dir - PAGE_OFFSET)
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}
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{
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moveli r3, CTX_PAGE_FLAG
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j _hv_install_context
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}
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1:
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/* Install the interrupt base. */
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moveli r0, hw2_last(intrpt_start)
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shl16insli r0, r0, hw1(intrpt_start)
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shl16insli r0, r0, hw0(intrpt_start)
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mtspr SPR_INTERRUPT_VECTOR_BASE_K, r0
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/* Get our processor number and save it away in SAVE_K_0. */
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jal _hv_inquire_topology
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{
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GET_FIRST_INT(r5, r1) /* r5 = width */
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GET_SECOND_INT(r4, r0) /* r4 = y */
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}
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{
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GET_FIRST_INT(r6, r0) /* r6 = x */
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mul_lu_lu r4, r4, r5
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}
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{
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add r4, r4, r6 /* r4 == cpu == y*width + x */
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}
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#ifdef CONFIG_SMP
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/*
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* Load up our per-cpu offset. When the first (master) tile
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* boots, this value is still zero, so we will load boot_pc
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* with start_kernel, and boot_sp with at the top of init_stack.
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* The master tile initializes the per-cpu offset array, so that
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* when subsequent (secondary) tiles boot, they will instead load
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* from their per-cpu versions of boot_sp and boot_pc.
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*/
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moveli r5, hw2_last(__per_cpu_offset)
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shl16insli r5, r5, hw1(__per_cpu_offset)
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shl16insli r5, r5, hw0(__per_cpu_offset)
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shl3add r5, r4, r5
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ld r5, r5
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bnez r5, 1f
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/*
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* Save the width and height to the smp_topology variable
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* for later use.
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*/
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moveli r0, hw2_last(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
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shl16insli r0, r0, hw1(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
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shl16insli r0, r0, hw0(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
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st r0, r1
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1:
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#else
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move r5, zero
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#endif
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/* Load and go with the correct pc and sp. */
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{
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moveli r1, hw2_last(boot_sp)
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moveli r0, hw2_last(boot_pc)
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}
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{
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shl16insli r1, r1, hw1(boot_sp)
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shl16insli r0, r0, hw1(boot_pc)
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}
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{
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shl16insli r1, r1, hw0(boot_sp)
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shl16insli r0, r0, hw0(boot_pc)
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}
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{
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add r1, r1, r5
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add r0, r0, r5
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}
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ld r0, r0
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ld sp, r1
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shli r4, r4, CPU_SHIFT
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bfins r4, sp, 0, CPU_SHIFT-1
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mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
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{
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move lr, zero /* stop backtraces in the called function */
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jr r0
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}
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ENDPROC(_start)
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__PAGE_ALIGNED_BSS
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.align PAGE_SIZE
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ENTRY(empty_zero_page)
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.fill PAGE_SIZE,1,0
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END(empty_zero_page)
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.macro PTE cpa, bits1
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.quad HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED |\
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HV_PTE_GLOBAL | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE) |\
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(\bits1) | (HV_CPA_TO_PTFN(\cpa) << HV_PTE_INDEX_PTFN)
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.endm
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__PAGE_ALIGNED_DATA
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.align PAGE_SIZE
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ENTRY(swapper_pg_dir)
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.org swapper_pg_dir + PGD_INDEX(PAGE_OFFSET) * HV_PTE_SIZE
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.Lsv_data_pmd:
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.quad 0 /* PTE temp_data_pmd - PAGE_OFFSET, 0 */
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.org swapper_pg_dir + PGD_INDEX(MEM_SV_START) * HV_PTE_SIZE
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.Lsv_code_pmd:
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.quad 0 /* PTE temp_code_pmd - PAGE_OFFSET, 0 */
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.org swapper_pg_dir + SIZEOF_PGD
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END(swapper_pg_dir)
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.align HV_PAGE_TABLE_ALIGN
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ENTRY(temp_data_pmd)
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/*
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* We fill the PAGE_OFFSET pmd with huge pages with
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* VA = PA + PAGE_OFFSET. We remap things with more precise access
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* permissions later.
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*/
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.set addr, 0
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.rept PTRS_PER_PMD
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PTE addr, HV_PTE_READABLE | HV_PTE_WRITABLE
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.set addr, addr + HPAGE_SIZE
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.endr
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.org temp_data_pmd + SIZEOF_PMD
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END(temp_data_pmd)
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.align HV_PAGE_TABLE_ALIGN
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ENTRY(temp_code_pmd)
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/*
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* We fill the MEM_SV_START pmd with huge pages with
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* VA = PA + PAGE_OFFSET. We remap things with more precise access
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* permissions later.
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*/
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.set addr, 0
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.rept PTRS_PER_PMD
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PTE addr, HV_PTE_READABLE | HV_PTE_EXECUTABLE
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.set addr, addr + HPAGE_SIZE
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.endr
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.org temp_code_pmd + SIZEOF_PMD
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END(temp_code_pmd)
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/*
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* Isolate swapper_pgprot to its own cache line, since each cpu
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* starting up will read it using VA-is-PA and local homing.
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* This would otherwise likely conflict with other data on the cache
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* line, once we have set its permanent home in the page tables.
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*/
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__INITDATA
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.align CHIP_L2_LINE_SIZE()
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ENTRY(swapper_pgprot)
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.quad HV_PTE_PRESENT | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
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.align CHIP_L2_LINE_SIZE()
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END(swapper_pgprot)
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