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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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37f3e0096f
The Denali NAND controller IP has separate reset control for the controller core and registers. Add the reset-names, and one more phandle accordingly. This is the approved DT-binding. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
610 lines
14 KiB
Plaintext
610 lines
14 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Device Tree Source for UniPhier Pro4 SoC
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//
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// Copyright (C) 2015-2016 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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/ {
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compatible = "socionext,uniphier-pro4";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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clocks {
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refclk: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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arm_timer_clk: arm-timer {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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<0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>;
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cache-unified;
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cache-size = <(768 * 1024)>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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spi0: spi@54006000 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006000 0x100>;
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interrupts = <0 39 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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resets = <&peri_rst 0>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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resets = <&peri_rst 1>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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resets = <&peri_rst 2>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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resets = <&peri_rst 3>;
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};
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gpio: gpio@55000000 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000000 0x200>;
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interrupt-parent = <&aidet>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 0>;
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gpio-ranges-group-names = "gpio_range";
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ngpios = <248>;
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socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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resets = <&peri_rst 4>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58781000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&peri_clk 5>;
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resets = <&peri_rst 5>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58782000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58782000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&peri_clk 6>;
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resets = <&peri_rst 6>;
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clock-frequency = <100000>;
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};
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i2c3: i2c@58783000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58783000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&peri_clk 7>;
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resets = <&peri_rst 7>;
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clock-frequency = <100000>;
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};
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/* i2c4 does not exist */
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/* chip-internal connection for DMD */
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i2c5: i2c@58785000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58785000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 25 4>;
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clocks = <&peri_clk 9>;
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resets = <&peri_rst 9>;
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clock-frequency = <400000>;
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};
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/* chip-internal connection for HDMI */
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i2c6: i2c@58786000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58786000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 26 4>;
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clocks = <&peri_clk 10>;
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resets = <&peri_rst 10>;
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clock-frequency = <400000>;
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};
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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status = "disabled";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_system_bus>;
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};
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smpctrl@59801000 {
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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mioctrl@59810000 {
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compatible = "socionext,uniphier-pro4-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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mio_clk: clock {
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compatible = "socionext,uniphier-pro4-mio-clock";
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#clock-cells = <1>;
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};
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mio_rst: reset {
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compatible = "socionext,uniphier-pro4-mio-reset";
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#reset-cells = <1>;
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};
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};
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perictrl@59820000 {
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compatible = "socionext,uniphier-pro4-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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peri_clk: clock {
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compatible = "socionext,uniphier-pro4-peri-clock";
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#clock-cells = <1>;
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};
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peri_rst: reset {
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compatible = "socionext,uniphier-pro4-peri-reset";
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#reset-cells = <1>;
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};
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};
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dmac: dma-controller@5a000000 {
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compatible = "socionext,uniphier-mio-dmac";
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reg = <0x5a000000 0x1000>;
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interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
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<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
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clocks = <&mio_clk 7>;
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resets = <&mio_rst 7>;
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#dma-cells = <1>;
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};
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sd: sdhc@5a400000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a400000 0x200>;
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interrupts = <0 76 4>;
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pinctrl-names = "default", "uhs";
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pinctrl-0 = <&pinctrl_sd>;
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pinctrl-1 = <&pinctrl_sd_uhs>;
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clocks = <&mio_clk 0>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 0>, <&mio_rst 3>;
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dma-names = "rx-tx";
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dmas = <&dmac 4>;
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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};
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emmc: sdhc@5a500000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a500000 0x200>;
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interrupts = <0 78 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc>;
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clocks = <&mio_clk 1>;
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reset-names = "host", "bridge", "hw";
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resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
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dma-names = "rx-tx";
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dmas = <&dmac 5>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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non-removable;
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};
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sd1: sdhc@5a600000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a600000 0x200>;
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interrupts = <0 85 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sd1>;
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clocks = <&mio_clk 2>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 2>, <&mio_rst 5>;
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dma-names = "rx-tx";
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dmas = <&dmac 6>;
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bus-width = <4>;
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cap-sd-highspeed;
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};
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usb2: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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interrupts = <0 80 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
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<&mio_clk 12>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
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<&mio_rst 12>;
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phy-names = "usb";
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phys = <&usb_phy0>;
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has-transaction-translator;
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};
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usb3: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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interrupts = <0 81 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb3>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
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<&mio_clk 13>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
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<&mio_rst 13>;
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phy-names = "usb";
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phys = <&usb_phy1>;
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has-transaction-translator;
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};
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soc_glue: soc-glue@5f800000 {
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compatible = "socionext,uniphier-pro4-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-pro4-pinctrl";
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};
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usb-phy {
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compatible = "socionext,uniphier-pro4-usb2-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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usb_phy0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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usb_phy1: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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usb_phy2: phy@2 {
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reg = <2>;
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#phy-cells = <0>;
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vbus-supply = <&usb0_vbus>;
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};
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usb_phy3: phy@3 {
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reg = <3>;
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#phy-cells = <0>;
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vbus-supply = <&usb1_vbus>;
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};
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};
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};
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soc-glue@5f900000 {
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compatible = "socionext,uniphier-pro4-soc-glue-debug",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x5f900000 0x2000>;
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efuse@100 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x100 0x28>;
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};
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efuse@130 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x130 0x8>;
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};
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efuse@200 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x200 0x14>;
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};
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};
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aidet: aidet@5fc20000 {
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compatible = "socionext,uniphier-pro4-aidet";
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reg = <0x5fc20000 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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timer@60000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x60000200 0x20>;
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interrupts = <1 11 0x304>;
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clocks = <&arm_timer_clk>;
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};
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timer@60000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x60000600 0x20>;
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interrupts = <1 13 0x304>;
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clocks = <&arm_timer_clk>;
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};
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intc: interrupt-controller@60001000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0x60001000 0x1000>,
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<0x60000100 0x100>;
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#interrupt-cells = <3>;
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interrupt-controller;
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};
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sysctrl@61840000 {
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compatible = "socionext,uniphier-pro4-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x10000>;
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sys_clk: clock {
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compatible = "socionext,uniphier-pro4-clock";
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#clock-cells = <1>;
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};
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sys_rst: reset {
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compatible = "socionext,uniphier-pro4-reset";
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#reset-cells = <1>;
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};
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};
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eth: ethernet@65000000 {
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compatible = "socionext,uniphier-pro4-ave4";
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status = "disabled";
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reg = <0x65000000 0x8500>;
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interrupts = <0 66 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ether_rgmii>;
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clock-names = "gio", "ether", "ether-gb", "ether-phy";
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clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
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<&sys_clk 10>;
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reset-names = "gio", "ether";
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resets = <&sys_rst 12>, <&sys_rst 6>;
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phy-mode = "rgmii";
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local-mac-address = [00 00 00 00 00 00];
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socionext,syscon-phy-mode = <&soc_glue 0>;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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usb0: usb@65a00000 {
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65a00000 0xcd00>;
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interrupt-names = "host", "peripheral";
|
|
interrupts = <0 134 4>, <0 135 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb0>;
|
|
clock-names = "ref", "bus_early", "suspend";
|
|
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
|
|
resets = <&usb0_rst 4>;
|
|
phys = <&usb_phy2>, <&usb0_ssphy>;
|
|
dr_mode = "host";
|
|
};
|
|
|
|
usb-glue@65b00000 {
|
|
compatible = "socionext,uniphier-pro4-dwc3-glue",
|
|
"simple-mfd";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x65b00000 0x100>;
|
|
|
|
usb0_vbus: regulator@0 {
|
|
compatible = "socionext,uniphier-pro4-usb3-regulator";
|
|
reg = <0 0x10>;
|
|
clock-names = "gio", "link";
|
|
clocks = <&sys_clk 12>, <&sys_clk 14>;
|
|
reset-names = "gio", "link";
|
|
resets = <&sys_rst 12>, <&sys_rst 14>;
|
|
};
|
|
|
|
usb0_ssphy: ss-phy@10 {
|
|
compatible = "socionext,uniphier-pro4-usb3-ssphy";
|
|
reg = <0x10 0x10>;
|
|
#phy-cells = <0>;
|
|
clock-names = "gio", "link";
|
|
clocks = <&sys_clk 12>, <&sys_clk 14>;
|
|
reset-names = "gio", "link";
|
|
resets = <&sys_rst 12>, <&sys_rst 14>;
|
|
vbus-supply = <&usb0_vbus>;
|
|
};
|
|
|
|
usb0_rst: reset@40 {
|
|
compatible = "socionext,uniphier-pro4-usb3-reset";
|
|
reg = <0x40 0x4>;
|
|
#reset-cells = <1>;
|
|
clock-names = "gio", "link";
|
|
clocks = <&sys_clk 12>, <&sys_clk 14>;
|
|
reset-names = "gio", "link";
|
|
resets = <&sys_rst 12>, <&sys_rst 14>;
|
|
};
|
|
};
|
|
|
|
usb1: usb@65c00000 {
|
|
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
|
status = "disabled";
|
|
reg = <0x65c00000 0xcd00>;
|
|
interrupt-names = "host", "peripheral";
|
|
interrupts = <0 137 4>, <0 138 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb1>;
|
|
clock-names = "ref", "bus_early", "suspend";
|
|
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
|
|
resets = <&usb1_rst 4>;
|
|
phys = <&usb_phy3>;
|
|
dr_mode = "host";
|
|
};
|
|
|
|
usb-glue@65d00000 {
|
|
compatible = "socionext,uniphier-pro4-dwc3-glue",
|
|
"simple-mfd";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x65d00000 0x100>;
|
|
|
|
usb1_vbus: regulator@0 {
|
|
compatible = "socionext,uniphier-pro4-usb3-regulator";
|
|
reg = <0 0x10>;
|
|
clock-names = "gio", "link";
|
|
clocks = <&sys_clk 12>, <&sys_clk 15>;
|
|
reset-names = "gio", "link";
|
|
resets = <&sys_rst 12>, <&sys_rst 15>;
|
|
};
|
|
|
|
usb1_rst: reset@40 {
|
|
compatible = "socionext,uniphier-pro4-usb3-reset";
|
|
reg = <0x40 0x4>;
|
|
#reset-cells = <1>;
|
|
clock-names = "gio", "link";
|
|
clocks = <&sys_clk 12>, <&sys_clk 15>;
|
|
reset-names = "gio", "link";
|
|
resets = <&sys_rst 12>, <&sys_rst 15>;
|
|
};
|
|
};
|
|
|
|
nand: nand@68000000 {
|
|
compatible = "socionext,uniphier-denali-nand-v5a";
|
|
status = "disabled";
|
|
reg-names = "nand_data", "denali_reg";
|
|
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 65 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand>;
|
|
clock-names = "nand", "nand_x", "ecc";
|
|
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
|
reset-names = "nand", "reg";
|
|
resets = <&sys_rst 2>, <&sys_rst 2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "uniphier-pinctrl.dtsi"
|