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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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19d52e94e0
This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl4rTjIRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXNPIxAAsx6cR/yzoEvUv1fGFi44Y/VZEhfI/8yT 5esGWql/UINkyTLBTsME6liDTt7rAVxcHH1JQj04hYH/w/PQU8S4iu8ZVwxoAb9R Mmnfn8Py26scney0zseJc6tTTDbtXF+mxDBYUqAJNKjDyoRkJKxWtMMOHUC7WjVW P5E4uWgi2ydEFgn6hOzLORgHPtNnOWPdXYzKvmum7VZdRny7KHcuOk4kVFnj3dzG RwGrsOQcs2EyHd08n+U3tZqk34JqhOWi2VAKPZTHVlsZOdDKU9hm45ZSDh/j7Xoy 74x2ux81guKBAtgpKSJR5TUottgPM5IdnnyCmKkDgF7AWySByeJYPOVWyxwZuSQD tCmCi9fFSXCogoijMvSFPbcsKI/u6UKHYIOS9zvJo70FxNVTckhzjTH+DRQpjrTB oEAfpCS56bHUUYvPomDvxRT87kLlcs/A6g8+puRKd2xa3dmsXkTKeppuEBIC6WKE JtZYGsvWSe0gSVscsrE3Ecf17jS2O7Yhy3/4eOHJzUgsIGn8xcjuJJO3Av+bFj87 kDF66tRKR6LcKD1S6v5a87hmKD3rxkj23LUEvS0bWsOVLmgqIQYeZYpR5ujkRLxC 1NlzWFVqBtCMe6qPRz7FaitrdZlTaMURRD0GXSQmZCsTrSVrghUTJBZw92ep2kWD rIwSzpB1p08= =u4PK -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late Late omap dts changes for v5.6 merge window This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. * tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits) ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt ARM: dts: Configure interconnect target module for am437x sgx ARM: dts: Configure sgx for dra7 ARM: dts: Configure rstctrl reset for am335x SGX ARM: dts: dra7: Add ti-sysc node for VPE ARM: dts: dra7: add vpe clkctrl node ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries ARM: dts: am43xx: add support for clkout1 clock arm: dts: dra76-evm: Add CAL and OV5640 nodes arm: dtsi: dra76x: Add CAL dtsi node arm: dts: dra72-evm-common: Add entries for the CSI2 cameras ARM: dts: DRA72: Add CAL dtsi node ARM: dts: dra7-l4: Add ti-sysc node for CAM ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only ARM: dts: dra7: add cam clkctrl node ARM: dts: Add omap3-echo ARM: dts: Add dtsi files for AM3703, AM3715 and DM3725 ARM: dts: am335x-icev2: Add support for OSD9616P0899-10 at i2c0 ... Link: https://lore.kernel.org/r/pull-1579896427-50330@atomide.com-3 Signed-off-by: Olof Johansson <olof@lixom.net>
499 lines
12 KiB
Plaintext
499 lines
12 KiB
Plaintext
/*
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* Device Tree Source for AM4372 SoC
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/am4.h>
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/ {
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compatible = "ti,am4372", "ti,am43";
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interrupt-parent = <&wakeupgen>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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memory@0 {
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device_type = "memory";
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reg = <0 0>;
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};
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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ethernet0 = &cpsw_emac0;
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ethernet1 = &cpsw_emac1;
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spi0 = &qspi;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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clock-latency = <300000>; /* From omap-cpufreq driver */
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};
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};
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cpu0_opp_table: opp-table {
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compatible = "operating-points-v2-ti-cpu";
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syscon = <&scm_conf>;
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opp50-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <950000 931000 969000>;
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opp-supported-hw = <0xFF 0x01>;
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opp-suspend;
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};
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opp100-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0xFF 0x04>;
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};
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opp120-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <1200000 1176000 1224000>;
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opp-supported-hw = <0xFF 0x08>;
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};
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oppturbo-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1260000 1234800 1285200>;
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opp-supported-hw = <0xFF 0x10>;
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};
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oppnitro-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1325000 1298500 1351500>;
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opp-supported-hw = <0xFF 0x20>;
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};
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};
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap4-mpu";
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ti,hwmods = "mpu";
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pm-sram = <&pm_sram_code
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&pm_sram_data>;
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};
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};
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gic: interrupt-controller@48241000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48241000 0x1000>,
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<0x48240100 0x0100>;
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interrupt-parent = <&gic>;
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};
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wakeupgen: interrupt-controller@48281000 {
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compatible = "ti,omap4-wugen-mpu";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48281000 0x1000>;
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interrupt-parent = <&gic>;
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};
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scu: scu@48240000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x48240000 0x100>;
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};
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global_timer: timer@48240200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x48240200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&gic>;
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clocks = <&mpu_periphclk>;
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};
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local_timer: timer@48240600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x48240600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&gic>;
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clocks = <&mpu_periphclk>;
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};
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l2-cache-controller@48242000 {
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compatible = "arm,pl310-cache";
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reg = <0x48242000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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ocp@44000000 {
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compatible = "ti,am4372-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main";
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ti,no-idle;
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reg = <0x44000000 0x400000
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0x44800000 0x400000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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l4_wkup: interconnect@44c00000 {
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wkup_m3: wkup_m3@100000 {
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compatible = "ti,am4372-wkup-m3";
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reg = <0x100000 0x4000>,
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<0x180000 0x2000>;
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reg-names = "umem", "dmem";
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ti,hwmods = "wkup_m3";
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ti,pm-firmware = "am335x-pm-firmware.elf";
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};
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};
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l4_per: interconnect@48000000 {
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};
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l4_fast: interconnect@4a000000 {
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};
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emif: emif@4c000000 {
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compatible = "ti,emif-am4372";
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reg = <0x4c000000 0x1000000>;
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ti,hwmods = "emif";
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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ti,no-idle;
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sram = <&pm_sram_code
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&pm_sram_data>;
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};
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edma: edma@49000000 {
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compatible = "ti,edma3-tpcc";
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ti,hwmods = "tpcc";
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reg = <0x49000000 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 0>;
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ti,edma-memcpy-channels = <58 59>;
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};
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edma_tptc0: tptc@49800000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc0";
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reg = <0x49800000 0x100000>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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edma_tptc1: tptc@49900000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc1";
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reg = <0x49900000 0x100000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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edma_tptc2: tptc@49a00000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc2";
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reg = <0x49a00000 0x100000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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target-module@47810000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x478102fc 0x4>,
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<0x47810110 0x4>,
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<0x47810114 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x47810000 0x1000>;
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mmc3: mmc@0 {
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compatible = "ti,omap4-hsmmc";
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ti,needs-special-reset;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x1000>;
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};
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};
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sham_target: target-module@53100000 {
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compatible = "ti,sysc-omap3-sham", "ti,sysc";
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reg = <0x53100100 0x4>,
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<0x53100110 0x4>,
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<0x53100114 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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/* Domains (P, C): per_pwrdm, l3_clkdm */
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clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x53100000 0x1000>;
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sham: sham@0 {
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compatible = "ti,omap5-sham";
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reg = <0 0x300>;
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dmas = <&edma 36 0>;
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dma-names = "rx";
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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aes_target: target-module@53501000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x53501080 0x4>,
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<0x53501084 0x4>,
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<0x53501088 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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/* Domains (P, C): per_pwrdm, l3_clkdm */
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clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x53501000 0x1000>;
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aes: aes@0 {
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compatible = "ti,omap4-aes";
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reg = <0 0xa0>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&edma 6 0>,
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<&edma 5 0>;
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dma-names = "tx", "rx";
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};
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};
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des_target: target-module@53701000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x53701030 0x4>,
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<0x53701034 0x4>,
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<0x53701038 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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/* Domains (P, C): per_pwrdm, l3_clkdm */
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clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x53701000 0x1000>;
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des: des@0 {
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compatible = "ti,omap4-des";
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reg = <0 0xa0>;
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interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&edma 34 0>,
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<&edma 33 0>;
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dma-names = "tx", "rx";
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};
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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dmas = <&edma 52 0>;
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dma-names = "rxtx";
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clocks = <&l3s_gclk>;
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clock-names = "fck";
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reg = <0x50000000 0x2000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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gpmc,num-cs = <7>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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target-module@47900000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x47900000 0x4>,
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<0x47900010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x47900000 0x1000>,
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<0x30000000 0x30000000 0x4000000>;
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qspi: spi@0 {
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compatible = "ti,am4372-qspi";
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reg = <0 0x100>,
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<0x30000000 0x4000000>;
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reg-names = "qspi_base", "qspi_mmap";
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clocks = <&dpll_per_m2_div4_ck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 138 0x4>;
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num-cs = <4>;
|
|
};
|
|
};
|
|
|
|
dss: dss@4832a000 {
|
|
compatible = "ti,omap3-dss";
|
|
reg = <0x4832a000 0x200>;
|
|
status = "disabled";
|
|
ti,hwmods = "dss_core";
|
|
clocks = <&disp_clk>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
dispc: dispc@4832a400 {
|
|
compatible = "ti,omap3-dispc";
|
|
reg = <0x4832a400 0x400>;
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "dss_dispc";
|
|
clocks = <&disp_clk>;
|
|
clock-names = "fck";
|
|
|
|
max-memory-bandwidth = <230000000>;
|
|
};
|
|
|
|
rfbi: rfbi@4832a800 {
|
|
compatible = "ti,omap3-rfbi";
|
|
reg = <0x4832a800 0x100>;
|
|
ti,hwmods = "dss_rfbi";
|
|
clocks = <&disp_clk>;
|
|
clock-names = "fck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
ocmcram: sram@40300000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x40300000 0x40000>; /* 256k */
|
|
ranges = <0x0 0x40300000 0x40000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
pm_sram_code: pm-code-sram@0 {
|
|
compatible = "ti,sram";
|
|
reg = <0x0 0x1000>;
|
|
protect-exec;
|
|
};
|
|
|
|
pm_sram_data: pm-data-sram@1000 {
|
|
compatible = "ti,sram";
|
|
reg = <0x1000 0x1000>;
|
|
pool;
|
|
};
|
|
};
|
|
|
|
target-module@56000000 {
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x5600fe00 0x4>,
|
|
<0x5600fe10 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
resets = <&prm_gfx 0>;
|
|
reset-names = "rstctrl";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x56000000 0x1000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "am437x-l4.dtsi"
|
|
#include "am43xx-clocks.dtsi"
|
|
|
|
&prcm {
|
|
prm_gfx: prm@400 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x400 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_per: prm@800 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x800 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_wkup: prm@2000 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x2000 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_device: prm@4000 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x4000 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|