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d492cccac2
For optimal performance, in a HW I/O coherency context such as the one used on Armada XP, the shared L2 bit of the CPU configuration register should be cleared. This commit adjusts the coherency fabric code used by Marvell EBU processors to clear this bit on Armada XP. Since it's a per-CPU register, it's cleared in set_cpu_coherent() for the boot CPU, and through a CPU notifier for the non-boot CPUs. [gregory.clement@free-electrons.com: rebasd on 4.3-rc1] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
21 lines
402 B
Plaintext
21 lines
402 B
Plaintext
MVEBU CPU Config registers
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MVEBU (Marvell SOCs: Armada 370/XP)
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Required properties:
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- compatible: one of:
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- "marvell,armada-370-cpu-config"
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- "marvell,armada-xp-cpu-config"
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- reg: Should contain CPU config registers location and length, in
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their per-CPU variant
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Example:
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cpu-config@21000 {
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compatible = "marvell,armada-xp-cpu-config";
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reg = <0x21000 0x8>;
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};
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