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1394f03221
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
171 lines
4.3 KiB
C
171 lines
4.3 KiB
C
/************************************************************
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*
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* Copyright (C) 2004, Analog Devices. All Rights Reserved
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*
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* FILE bfin5xx_spi.h
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* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
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*
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*
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* DATE OF CREATION: March. 10th 2006
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*
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* SYNOPSIS:
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*
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* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
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**************************************************************
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* MODIFICATION HISTORY:
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* March 10, 2006 bfin5xx_spi.h Created. (Luke Yang)
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************************************************************/
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#ifndef _SPI_CHANNEL_H_
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#define _SPI_CHANNEL_H_
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#define SPI0_REGBASE 0xffc00500
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#define SPI_READ 0
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#define SPI_WRITE 1
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#define SPI_CTRL_OFF 0x0
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#define SPI_FLAG_OFF 0x4
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#define SPI_STAT_OFF 0x8
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#define SPI_TXBUFF_OFF 0xc
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#define SPI_RXBUFF_OFF 0x10
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#define SPI_BAUD_OFF 0x14
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#define SPI_SHAW_OFF 0x18
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#define CMD_SPI_OUT_ENABLE 1
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#define CMD_SPI_SET_BAUDRATE 2
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#define CMD_SPI_SET_POLAR 3
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#define CMD_SPI_SET_PHASE 4
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#define CMD_SPI_SET_MASTER 5
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#define CMD_SPI_SET_SENDOPT 6
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#define CMD_SPI_SET_RECVOPT 7
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#define CMD_SPI_SET_ORDER 8
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#define CMD_SPI_SET_LENGTH16 9
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#define CMD_SPI_GET_STAT 11
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#define CMD_SPI_GET_CFG 12
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#define CMD_SPI_SET_CSAVAIL 13
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#define CMD_SPI_SET_CSHIGH 14 /* CS unavail */
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#define CMD_SPI_SET_CSLOW 15 /* CS avail */
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#define CMD_SPI_MISO_ENABLE 16
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#define CMD_SPI_SET_CSENABLE 17
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#define CMD_SPI_SET_CSDISABLE 18
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#define CMD_SPI_SET_TRIGGER_MODE 19
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#define CMD_SPI_SET_TRIGGER_SENSE 20
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#define CMD_SPI_SET_TRIGGER_EDGE 21
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#define CMD_SPI_SET_TRIGGER_LEVEL 22
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#define CMD_SPI_SET_TIME_SPS 23
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#define CMD_SPI_SET_TIME_SAMPLES 24
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#define CMD_SPI_GET_SYSTEMCLOCK 25
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#define CMD_SPI_SET_WRITECONTINUOUS 26
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#define CMD_SPI_SET_SKFS 27
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#define CMD_SPI_GET_ALLCONFIG 32 /* For debug */
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#define SPI_DEFAULT_BARD 0x0100
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#define SPI0_IRQ_NUM IRQ_SPI
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#define SPI_ERR_TRIG -1
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#define BIT_CTL_ENABLE 0x4000
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#define BIT_CTL_OPENDRAIN 0x2000
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#define BIT_CTL_MASTER 0x1000
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#define BIT_CTL_POLAR 0x0800
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#define BIT_CTL_PHASE 0x0400
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#define BIT_CTL_BITORDER 0x0200
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#define BIT_CTL_WORDSIZE 0x0100
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#define BIT_CTL_MISOENABLE 0x0020
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#define BIT_CTL_RXMOD 0x0000
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#define BIT_CTL_TXMOD 0x0001
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#define BIT_CTL_TIMOD_DMA_TX 0x0003
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#define BIT_CTL_TIMOD_DMA_RX 0x0002
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#define BIT_CTL_SENDOPT 0x0004
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#define BIT_CTL_TIMOD 0x0003
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#define BIT_STAT_SPIF 0x0001
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#define BIT_STAT_MODF 0x0002
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#define BIT_STAT_TXE 0x0004
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#define BIT_STAT_TXS 0x0008
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#define BIT_STAT_RBSY 0x0010
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#define BIT_STAT_RXS 0x0020
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#define BIT_STAT_TXCOL 0x0040
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#define BIT_STAT_CLR 0xFFFF
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#define BIT_STU_SENDOVER 0x0001
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#define BIT_STU_RECVFULL 0x0020
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#define CFG_SPI_ENABLE 1
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#define CFG_SPI_DISABLE 0
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#define CFG_SPI_OUTENABLE 1
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#define CFG_SPI_OUTDISABLE 0
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#define CFG_SPI_ACTLOW 1
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#define CFG_SPI_ACTHIGH 0
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#define CFG_SPI_PHASESTART 1
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#define CFG_SPI_PHASEMID 0
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#define CFG_SPI_MASTER 1
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#define CFG_SPI_SLAVE 0
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#define CFG_SPI_SENELAST 0
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#define CFG_SPI_SENDZERO 1
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#define CFG_SPI_RCVFLUSH 1
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#define CFG_SPI_RCVDISCARD 0
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#define CFG_SPI_LSBFIRST 1
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#define CFG_SPI_MSBFIRST 0
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#define CFG_SPI_WORDSIZE16 1
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#define CFG_SPI_WORDSIZE8 0
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#define CFG_SPI_MISOENABLE 1
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#define CFG_SPI_MISODISABLE 0
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#define CFG_SPI_READ 0x00
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#define CFG_SPI_WRITE 0x01
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#define CFG_SPI_DMAREAD 0x02
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#define CFG_SPI_DMAWRITE 0x03
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#define CFG_SPI_CSCLEARALL 0
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#define CFG_SPI_CHIPSEL1 1
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#define CFG_SPI_CHIPSEL2 2
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#define CFG_SPI_CHIPSEL3 3
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#define CFG_SPI_CHIPSEL4 4
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#define CFG_SPI_CHIPSEL5 5
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#define CFG_SPI_CHIPSEL6 6
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#define CFG_SPI_CHIPSEL7 7
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#define CFG_SPI_CS1VALUE 1
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#define CFG_SPI_CS2VALUE 2
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#define CFG_SPI_CS3VALUE 3
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#define CFG_SPI_CS4VALUE 4
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#define CFG_SPI_CS5VALUE 5
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#define CFG_SPI_CS6VALUE 6
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#define CFG_SPI_CS7VALUE 7
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/* device.platform_data for SSP controller devices */
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struct bfin5xx_spi_master {
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u16 num_chipselect;
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u8 enable_dma;
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};
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/* spi_board_info.controller_data for SPI slave devices,
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* copied to spi_device.platform_data ... mostly for dma tuning
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*/
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struct bfin5xx_spi_chip {
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u16 ctl_reg;
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u8 enable_dma;
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u8 bits_per_word;
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u8 cs_change_per_word;
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u8 cs_chg_udelay;
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};
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#endif /* _SPI_CHANNEL_H_ */
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