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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 15:42:49 +07:00
c709ddfac8
As explained in Documentation/devicetree/bindings/net/fsl-fec.txt the phy-reset-gpios is active high only if the 'phy-reset-active-high' is present. As 'phy-reset-active-high' is not used here, fix the device tree description by passing GPIO_ACTIVE_LOW flag. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Patrick Bruenn <p.bruenn@beckhoff.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
298 lines
6.5 KiB
Plaintext
298 lines
6.5 KiB
Plaintext
/*
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* Copyright 2017 Beckhoff Automation GmbH & Co. KG
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* based on imx53-qsb.dts
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx53.dtsi"
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/ {
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model = "Beckhoff CX9020 Embedded PC";
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compatible = "bhf,cx9020", "fsl,imx53";
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chosen {
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stdout-path = &uart2;
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};
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memory {
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reg = <0x70000000 0x20000000>,
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<0xb0000000 0x20000000>;
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};
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display-0 {
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#address-cells =<1>;
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#size-cells = <0>;
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compatible = "fsl,imx-parallel-display";
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interface-pix-fmt = "rgb24";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu_disp0>;
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port@0 {
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reg = <0>;
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display0_in: endpoint {
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remote-endpoint = <&ipu_di0_disp0>;
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};
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};
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port@1 {
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reg = <1>;
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display0_out: endpoint {
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remote-endpoint = <&tfp410_in>;
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};
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};
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};
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dvi-connector {
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compatible = "dvi-connector";
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ddc-i2c-bus = <&i2c2>;
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digital;
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port {
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dvi_connector_in: endpoint {
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remote-endpoint = <&tfp410_out>;
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};
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};
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};
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dvi-converter {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "ti,tfp410";
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port@0 {
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reg = <0>;
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tfp410_in: endpoint {
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remote-endpoint = <&display0_out>;
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};
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};
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port@1 {
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reg = <1>;
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tfp410_out: endpoint {
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remote-endpoint = <&dvi_connector_in>;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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pwr-r {
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gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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pwr-g {
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gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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pwr-b {
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gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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sd1-b {
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linux,default-trigger = "mmc0";
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gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
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};
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sd2-b {
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linux,default-trigger = "mmc1";
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gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
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};
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};
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regulator-3p2v {
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compatible = "regulator-fixed";
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regulator-name = "3P2V";
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regulator-min-microvolt = <3200000>;
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regulator-max-microvolt = <3200000>;
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regulator-always-on;
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};
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reg_usb_vbus: regulator-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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status = "okay";
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};
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&esdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc2>;
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cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&ipu_di0_disp0 {
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remote-endpoint = <&display0_in>;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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fsl,dte-mode;
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status = "okay";
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};
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&usbh1 {
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vbus-supply = <®_usb_vbus>;
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phy_type = "utmi";
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status = "okay";
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};
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&usbotg {
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dr_mode = "peripheral";
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status = "okay";
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};
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&vpu {
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX53_PAD_GPIO_0__CCM_CLKO 0x1c4
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MX53_PAD_GPIO_16__I2C3_SDA 0x1c4
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MX53_PAD_EIM_D22__GPIO3_22 0x1c4
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MX53_PAD_EIM_D23__GPIO3_23 0x1e4
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MX53_PAD_EIM_D24__GPIO3_24 0x1e4
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>;
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};
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
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MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
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MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
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MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
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MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
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MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
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MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4
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MX53_PAD_EIM_D17__GPIO3_17 0x1e4
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MX53_PAD_GPIO_3__GPIO1_3 0x1c4
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>;
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};
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pinctrl_esdhc2: esdhc2grp {
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fsl,pins = <
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MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
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MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
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MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
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MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
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MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
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MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
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MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4
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MX53_PAD_EIM_D20__GPIO3_20 0x1e4
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MX53_PAD_GPIO_8__GPIO1_8 0x1c4
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX53_PAD_FEC_MDC__FEC_MDC 0x4
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
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MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
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>;
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};
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pinctrl_ipu_disp0: ipudisp0grp {
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fsl,pins = <
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MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
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MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
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MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
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MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
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MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
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MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
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MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
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MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
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MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
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MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
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MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
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MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
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MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
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MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
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MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
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MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
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MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
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MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
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MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
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MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
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MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
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MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
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MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
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MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
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MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
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MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
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MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
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MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
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MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
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MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
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MX53_PAD_EIM_D28__UART2_RTS 0x1e4
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MX53_PAD_EIM_D29__UART2_CTS 0x1e4
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>;
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};
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};
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