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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 15:27:36 +07:00
b03781920c
* clk-mediatek: clk: mediatek: add audsys support for MT2701 clk: mediatek: add devm_of_platform_populate() for MT7622 audsys dt-bindings: clock: mediatek: add audsys support for MT2701 dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device clk: mediatek: update missing clock data for MT7622 audsys clk: mediatek: fix PWM clock source by adding a fixed-factor clock dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4 * clk-hisi: clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc() clk: hisilicon: mark wdt_mux_p[] as const clk: hisilicon: Mark phase_ops static clk: hi3798cv200: add emmc sample and drive clock clk: hisilicon: add hisi phase clock support clk: hi3798cv200: add COMBPHY0 clock support clk: hi3798cv200: fix define indentation clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK clk: hi3798cv200: correct IR clock parent clk: hi3798cv200: fix unregister call sequence in error path * clk-allwinner: clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU clk: sunxi-ng: add support for the Allwinner H6 CCU dt-bindings: add device tree binding for Allwinner H6 main CCU clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate clk: sunxi-ng: h3: h5: Add minimal rate for video PLL clk: sunxi-ng: Add check for minimal rate to NM PLLs clk: sunxi-ng: Use u64 for calculation of nkmp rate clk: sunxi-ng: Mask nkmp factors when setting register clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name * clk-ux500: clk: ux500: Drop AB8540/9540 support * clk-renesas: (27 commits) clk: renesas: cpg-mssr: Adjust r8a77980 ifdef clk: renesas: rcar-gen3: Always use readl()/writel() clk: renesas: sh73a0: Always use readl()/writel() clk: renesas: rza1: Always use readl()/writel() clk: renesas: rcar-gen2: Always use readl()/writel() clk: renesas: r8a7740: Always use readl()/writel() clk: renesas: r8a73a4: Always use readl()/writel() clk: renesas: mstp: Always use readl()/writel() clk: renesas: div6: Always use readl()/writel() clk: fix false-positive Wmaybe-uninitialized warning clk: renesas: r8a77965: Replace DU2 clock clk: renesas: cpg-mssr: Add support for R-Car M3-N clk: renesas: cpg-mssr: add R8A77980 support dt-bindings: clock: add R8A77980 CPG core clock definitions clk: renesas: r8a7792: Add rwdt clock clk: renesas: r8a7794: Add rwdt clock clk: renesas: r8a7791/r8a7793: Add rwdt clock clk: renesas: r8a7790: Add rwdt clock clk: renesas: r8a7745: Add rwdt clock clk: renesas: r8a7743: Add rwdt clock ... |
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|---|---|---|
| .. | ||
| clk-apmixed.c | ||
| clk-cpumux.c | ||
| clk-cpumux.h | ||
| clk-gate.c | ||
| clk-gate.h | ||
| clk-mt2701-aud.c | ||
| clk-mt2701-bdp.c | ||
| clk-mt2701-eth.c | ||
| clk-mt2701-hif.c | ||
| clk-mt2701-img.c | ||
| clk-mt2701-mm.c | ||
| clk-mt2701-vdec.c | ||
| clk-mt2701.c | ||
| clk-mt2712-bdp.c | ||
| clk-mt2712-img.c | ||
| clk-mt2712-jpgdec.c | ||
| clk-mt2712-mfg.c | ||
| clk-mt2712-mm.c | ||
| clk-mt2712-vdec.c | ||
| clk-mt2712-venc.c | ||
| clk-mt2712.c | ||
| clk-mt6797-img.c | ||
| clk-mt6797-mm.c | ||
| clk-mt6797-vdec.c | ||
| clk-mt6797-venc.c | ||
| clk-mt6797.c | ||
| clk-mt7622-aud.c | ||
| clk-mt7622-eth.c | ||
| clk-mt7622-hif.c | ||
| clk-mt7622.c | ||
| clk-mt8135.c | ||
| clk-mt8173.c | ||
| clk-mtk.c | ||
| clk-mtk.h | ||
| clk-pll.c | ||
| Kconfig | ||
| Makefile | ||
| reset.c | ||