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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 03:35:27 +07:00
b0ffeb537f
Number of outstanding_pi may overflow and as a result may indicate that
there are no elements in the queue. The effect of doing this is that the
MAD layer will get stuck waiting for completions. The MAD layer will
think that the QP is full - because it didn't receive these completions.
This fix changes it so the outstanding_pi number is increased
with 32-bit wraparound and is not limited to max_send_wr so
that the difference between outstanding_pi and outstanding_ci will
really indicate the number of outstanding completions.
Cc: Stable <stable@vger.kernel.org>
Fixes: ea6dc20362
('IB/mlx5: Reorder GSI completions')
Signed-off-by: Slava Shwartsman <slavash@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Reviewed-by: Haggai Eran <haggaie@mellanox.com>
Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Doug Ledford <dledford@redhat.com>
542 lines
13 KiB
C
542 lines
13 KiB
C
/*
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* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "mlx5_ib.h"
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struct mlx5_ib_gsi_wr {
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struct ib_cqe cqe;
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struct ib_wc wc;
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int send_flags;
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bool completed:1;
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};
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struct mlx5_ib_gsi_qp {
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struct ib_qp ibqp;
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struct ib_qp *rx_qp;
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u8 port_num;
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struct ib_qp_cap cap;
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enum ib_sig_type sq_sig_type;
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/* Serialize qp state modifications */
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struct mutex mutex;
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struct ib_cq *cq;
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struct mlx5_ib_gsi_wr *outstanding_wrs;
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u32 outstanding_pi, outstanding_ci;
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int num_qps;
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/* Protects access to the tx_qps. Post send operations synchronize
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* with tx_qp creation in setup_qp(). Also protects the
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* outstanding_wrs array and indices.
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*/
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spinlock_t lock;
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struct ib_qp **tx_qps;
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};
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static struct mlx5_ib_gsi_qp *gsi_qp(struct ib_qp *qp)
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{
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return container_of(qp, struct mlx5_ib_gsi_qp, ibqp);
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}
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static bool mlx5_ib_deth_sqpn_cap(struct mlx5_ib_dev *dev)
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{
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return MLX5_CAP_GEN(dev->mdev, set_deth_sqpn);
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}
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/* Call with gsi->lock locked */
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static void generate_completions(struct mlx5_ib_gsi_qp *gsi)
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{
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struct ib_cq *gsi_cq = gsi->ibqp.send_cq;
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struct mlx5_ib_gsi_wr *wr;
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u32 index;
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for (index = gsi->outstanding_ci; index != gsi->outstanding_pi;
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index++) {
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wr = &gsi->outstanding_wrs[index % gsi->cap.max_send_wr];
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if (!wr->completed)
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break;
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if (gsi->sq_sig_type == IB_SIGNAL_ALL_WR ||
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wr->send_flags & IB_SEND_SIGNALED)
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WARN_ON_ONCE(mlx5_ib_generate_wc(gsi_cq, &wr->wc));
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wr->completed = false;
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}
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gsi->outstanding_ci = index;
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}
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static void handle_single_completion(struct ib_cq *cq, struct ib_wc *wc)
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{
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struct mlx5_ib_gsi_qp *gsi = cq->cq_context;
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struct mlx5_ib_gsi_wr *wr =
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container_of(wc->wr_cqe, struct mlx5_ib_gsi_wr, cqe);
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u64 wr_id;
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unsigned long flags;
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spin_lock_irqsave(&gsi->lock, flags);
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wr->completed = true;
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wr_id = wr->wc.wr_id;
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wr->wc = *wc;
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wr->wc.wr_id = wr_id;
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wr->wc.qp = &gsi->ibqp;
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generate_completions(gsi);
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spin_unlock_irqrestore(&gsi->lock, flags);
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}
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struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
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struct ib_qp_init_attr *init_attr)
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{
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struct mlx5_ib_dev *dev = to_mdev(pd->device);
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struct mlx5_ib_gsi_qp *gsi;
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struct ib_qp_init_attr hw_init_attr = *init_attr;
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const u8 port_num = init_attr->port_num;
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const int num_pkeys = pd->device->attrs.max_pkeys;
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const int num_qps = mlx5_ib_deth_sqpn_cap(dev) ? num_pkeys : 0;
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int ret;
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mlx5_ib_dbg(dev, "creating GSI QP\n");
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if (port_num > ARRAY_SIZE(dev->devr.ports) || port_num < 1) {
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mlx5_ib_warn(dev,
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"invalid port number %d during GSI QP creation\n",
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port_num);
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return ERR_PTR(-EINVAL);
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}
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gsi = kzalloc(sizeof(*gsi), GFP_KERNEL);
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if (!gsi)
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return ERR_PTR(-ENOMEM);
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gsi->tx_qps = kcalloc(num_qps, sizeof(*gsi->tx_qps), GFP_KERNEL);
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if (!gsi->tx_qps) {
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ret = -ENOMEM;
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goto err_free;
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}
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gsi->outstanding_wrs = kcalloc(init_attr->cap.max_send_wr,
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sizeof(*gsi->outstanding_wrs),
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GFP_KERNEL);
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if (!gsi->outstanding_wrs) {
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ret = -ENOMEM;
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goto err_free_tx;
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}
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mutex_init(&gsi->mutex);
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mutex_lock(&dev->devr.mutex);
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if (dev->devr.ports[port_num - 1].gsi) {
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mlx5_ib_warn(dev, "GSI QP already exists on port %d\n",
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port_num);
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ret = -EBUSY;
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goto err_free_wrs;
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}
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gsi->num_qps = num_qps;
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spin_lock_init(&gsi->lock);
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gsi->cap = init_attr->cap;
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gsi->sq_sig_type = init_attr->sq_sig_type;
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gsi->ibqp.qp_num = 1;
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gsi->port_num = port_num;
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gsi->cq = ib_alloc_cq(pd->device, gsi, init_attr->cap.max_send_wr, 0,
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IB_POLL_SOFTIRQ);
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if (IS_ERR(gsi->cq)) {
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mlx5_ib_warn(dev, "unable to create send CQ for GSI QP. error %ld\n",
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PTR_ERR(gsi->cq));
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ret = PTR_ERR(gsi->cq);
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goto err_free_wrs;
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}
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hw_init_attr.qp_type = MLX5_IB_QPT_HW_GSI;
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hw_init_attr.send_cq = gsi->cq;
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if (num_qps) {
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hw_init_attr.cap.max_send_wr = 0;
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hw_init_attr.cap.max_send_sge = 0;
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hw_init_attr.cap.max_inline_data = 0;
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}
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gsi->rx_qp = ib_create_qp(pd, &hw_init_attr);
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if (IS_ERR(gsi->rx_qp)) {
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mlx5_ib_warn(dev, "unable to create hardware GSI QP. error %ld\n",
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PTR_ERR(gsi->rx_qp));
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ret = PTR_ERR(gsi->rx_qp);
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goto err_destroy_cq;
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}
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dev->devr.ports[init_attr->port_num - 1].gsi = gsi;
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mutex_unlock(&dev->devr.mutex);
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return &gsi->ibqp;
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err_destroy_cq:
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ib_free_cq(gsi->cq);
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err_free_wrs:
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mutex_unlock(&dev->devr.mutex);
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kfree(gsi->outstanding_wrs);
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err_free_tx:
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kfree(gsi->tx_qps);
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err_free:
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kfree(gsi);
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return ERR_PTR(ret);
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}
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int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp)
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{
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struct mlx5_ib_dev *dev = to_mdev(qp->device);
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struct mlx5_ib_gsi_qp *gsi = gsi_qp(qp);
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const int port_num = gsi->port_num;
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int qp_index;
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int ret;
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mlx5_ib_dbg(dev, "destroying GSI QP\n");
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mutex_lock(&dev->devr.mutex);
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ret = ib_destroy_qp(gsi->rx_qp);
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if (ret) {
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mlx5_ib_warn(dev, "unable to destroy hardware GSI QP. error %d\n",
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ret);
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mutex_unlock(&dev->devr.mutex);
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return ret;
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}
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dev->devr.ports[port_num - 1].gsi = NULL;
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mutex_unlock(&dev->devr.mutex);
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gsi->rx_qp = NULL;
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for (qp_index = 0; qp_index < gsi->num_qps; ++qp_index) {
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if (!gsi->tx_qps[qp_index])
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continue;
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WARN_ON_ONCE(ib_destroy_qp(gsi->tx_qps[qp_index]));
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gsi->tx_qps[qp_index] = NULL;
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}
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ib_free_cq(gsi->cq);
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kfree(gsi->outstanding_wrs);
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kfree(gsi->tx_qps);
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kfree(gsi);
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return 0;
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}
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static struct ib_qp *create_gsi_ud_qp(struct mlx5_ib_gsi_qp *gsi)
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{
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struct ib_pd *pd = gsi->rx_qp->pd;
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struct ib_qp_init_attr init_attr = {
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.event_handler = gsi->rx_qp->event_handler,
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.qp_context = gsi->rx_qp->qp_context,
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.send_cq = gsi->cq,
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.recv_cq = gsi->rx_qp->recv_cq,
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.cap = {
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.max_send_wr = gsi->cap.max_send_wr,
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.max_send_sge = gsi->cap.max_send_sge,
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.max_inline_data = gsi->cap.max_inline_data,
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},
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.sq_sig_type = gsi->sq_sig_type,
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.qp_type = IB_QPT_UD,
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.create_flags = mlx5_ib_create_qp_sqpn_qp1(),
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};
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return ib_create_qp(pd, &init_attr);
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}
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static int modify_to_rts(struct mlx5_ib_gsi_qp *gsi, struct ib_qp *qp,
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u16 qp_index)
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{
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struct mlx5_ib_dev *dev = to_mdev(qp->device);
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struct ib_qp_attr attr;
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int mask;
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int ret;
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mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY | IB_QP_PORT;
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attr.qp_state = IB_QPS_INIT;
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attr.pkey_index = qp_index;
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attr.qkey = IB_QP1_QKEY;
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attr.port_num = gsi->port_num;
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ret = ib_modify_qp(qp, &attr, mask);
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if (ret) {
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mlx5_ib_err(dev, "could not change QP%d state to INIT: %d\n",
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qp->qp_num, ret);
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return ret;
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}
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attr.qp_state = IB_QPS_RTR;
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ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
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if (ret) {
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mlx5_ib_err(dev, "could not change QP%d state to RTR: %d\n",
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qp->qp_num, ret);
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return ret;
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}
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attr.qp_state = IB_QPS_RTS;
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attr.sq_psn = 0;
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ret = ib_modify_qp(qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN);
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if (ret) {
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mlx5_ib_err(dev, "could not change QP%d state to RTS: %d\n",
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qp->qp_num, ret);
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return ret;
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}
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return 0;
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}
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static void setup_qp(struct mlx5_ib_gsi_qp *gsi, u16 qp_index)
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{
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struct ib_device *device = gsi->rx_qp->device;
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struct mlx5_ib_dev *dev = to_mdev(device);
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struct ib_qp *qp;
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unsigned long flags;
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u16 pkey;
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int ret;
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ret = ib_query_pkey(device, gsi->port_num, qp_index, &pkey);
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if (ret) {
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mlx5_ib_warn(dev, "unable to read P_Key at port %d, index %d\n",
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gsi->port_num, qp_index);
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return;
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}
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if (!pkey) {
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mlx5_ib_dbg(dev, "invalid P_Key at port %d, index %d. Skipping.\n",
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gsi->port_num, qp_index);
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return;
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}
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spin_lock_irqsave(&gsi->lock, flags);
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qp = gsi->tx_qps[qp_index];
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spin_unlock_irqrestore(&gsi->lock, flags);
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if (qp) {
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mlx5_ib_dbg(dev, "already existing GSI TX QP at port %d, index %d. Skipping\n",
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gsi->port_num, qp_index);
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return;
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}
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qp = create_gsi_ud_qp(gsi);
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if (IS_ERR(qp)) {
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mlx5_ib_warn(dev, "unable to create hardware UD QP for GSI: %ld\n",
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PTR_ERR(qp));
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return;
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}
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ret = modify_to_rts(gsi, qp, qp_index);
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if (ret)
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goto err_destroy_qp;
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spin_lock_irqsave(&gsi->lock, flags);
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WARN_ON_ONCE(gsi->tx_qps[qp_index]);
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gsi->tx_qps[qp_index] = qp;
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spin_unlock_irqrestore(&gsi->lock, flags);
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return;
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err_destroy_qp:
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WARN_ON_ONCE(qp);
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}
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static void setup_qps(struct mlx5_ib_gsi_qp *gsi)
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{
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u16 qp_index;
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for (qp_index = 0; qp_index < gsi->num_qps; ++qp_index)
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setup_qp(gsi, qp_index);
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}
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int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
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int attr_mask)
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{
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struct mlx5_ib_dev *dev = to_mdev(qp->device);
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struct mlx5_ib_gsi_qp *gsi = gsi_qp(qp);
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int ret;
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mlx5_ib_dbg(dev, "modifying GSI QP to state %d\n", attr->qp_state);
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mutex_lock(&gsi->mutex);
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ret = ib_modify_qp(gsi->rx_qp, attr, attr_mask);
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if (ret) {
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mlx5_ib_warn(dev, "unable to modify GSI rx QP: %d\n", ret);
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goto unlock;
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}
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if (to_mqp(gsi->rx_qp)->state == IB_QPS_RTS)
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setup_qps(gsi);
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unlock:
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mutex_unlock(&gsi->mutex);
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return ret;
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}
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int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
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int qp_attr_mask,
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struct ib_qp_init_attr *qp_init_attr)
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{
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struct mlx5_ib_gsi_qp *gsi = gsi_qp(qp);
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int ret;
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mutex_lock(&gsi->mutex);
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ret = ib_query_qp(gsi->rx_qp, qp_attr, qp_attr_mask, qp_init_attr);
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qp_init_attr->cap = gsi->cap;
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mutex_unlock(&gsi->mutex);
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return ret;
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}
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/* Call with gsi->lock locked */
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static int mlx5_ib_add_outstanding_wr(struct mlx5_ib_gsi_qp *gsi,
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struct ib_ud_wr *wr, struct ib_wc *wc)
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{
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struct mlx5_ib_dev *dev = to_mdev(gsi->rx_qp->device);
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struct mlx5_ib_gsi_wr *gsi_wr;
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if (gsi->outstanding_pi == gsi->outstanding_ci + gsi->cap.max_send_wr) {
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mlx5_ib_warn(dev, "no available GSI work request.\n");
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return -ENOMEM;
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}
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gsi_wr = &gsi->outstanding_wrs[gsi->outstanding_pi %
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gsi->cap.max_send_wr];
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gsi->outstanding_pi++;
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if (!wc) {
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memset(&gsi_wr->wc, 0, sizeof(gsi_wr->wc));
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gsi_wr->wc.pkey_index = wr->pkey_index;
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gsi_wr->wc.wr_id = wr->wr.wr_id;
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} else {
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gsi_wr->wc = *wc;
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gsi_wr->completed = true;
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}
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gsi_wr->cqe.done = &handle_single_completion;
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wr->wr.wr_cqe = &gsi_wr->cqe;
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return 0;
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}
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/* Call with gsi->lock locked */
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static int mlx5_ib_gsi_silent_drop(struct mlx5_ib_gsi_qp *gsi,
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struct ib_ud_wr *wr)
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{
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struct ib_wc wc = {
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{ .wr_id = wr->wr.wr_id },
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.status = IB_WC_SUCCESS,
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.opcode = IB_WC_SEND,
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.qp = &gsi->ibqp,
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};
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int ret;
|
|
|
|
ret = mlx5_ib_add_outstanding_wr(gsi, wr, &wc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
generate_completions(gsi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Call with gsi->lock locked */
|
|
static struct ib_qp *get_tx_qp(struct mlx5_ib_gsi_qp *gsi, struct ib_ud_wr *wr)
|
|
{
|
|
struct mlx5_ib_dev *dev = to_mdev(gsi->rx_qp->device);
|
|
int qp_index = wr->pkey_index;
|
|
|
|
if (!mlx5_ib_deth_sqpn_cap(dev))
|
|
return gsi->rx_qp;
|
|
|
|
if (qp_index >= gsi->num_qps)
|
|
return NULL;
|
|
|
|
return gsi->tx_qps[qp_index];
|
|
}
|
|
|
|
int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr,
|
|
struct ib_send_wr **bad_wr)
|
|
{
|
|
struct mlx5_ib_gsi_qp *gsi = gsi_qp(qp);
|
|
struct ib_qp *tx_qp;
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
for (; wr; wr = wr->next) {
|
|
struct ib_ud_wr cur_wr = *ud_wr(wr);
|
|
|
|
cur_wr.wr.next = NULL;
|
|
|
|
spin_lock_irqsave(&gsi->lock, flags);
|
|
tx_qp = get_tx_qp(gsi, &cur_wr);
|
|
if (!tx_qp) {
|
|
ret = mlx5_ib_gsi_silent_drop(gsi, &cur_wr);
|
|
if (ret)
|
|
goto err;
|
|
spin_unlock_irqrestore(&gsi->lock, flags);
|
|
continue;
|
|
}
|
|
|
|
ret = mlx5_ib_add_outstanding_wr(gsi, &cur_wr, NULL);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = ib_post_send(tx_qp, &cur_wr.wr, bad_wr);
|
|
if (ret) {
|
|
/* Undo the effect of adding the outstanding wr */
|
|
gsi->outstanding_pi = (gsi->outstanding_pi - 1) %
|
|
gsi->cap.max_send_wr;
|
|
goto err;
|
|
}
|
|
spin_unlock_irqrestore(&gsi->lock, flags);
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
spin_unlock_irqrestore(&gsi->lock, flags);
|
|
*bad_wr = wr;
|
|
return ret;
|
|
}
|
|
|
|
int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr,
|
|
struct ib_recv_wr **bad_wr)
|
|
{
|
|
struct mlx5_ib_gsi_qp *gsi = gsi_qp(qp);
|
|
|
|
return ib_post_recv(gsi->rx_qp, wr, bad_wr);
|
|
}
|
|
|
|
void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi)
|
|
{
|
|
if (!gsi)
|
|
return;
|
|
|
|
mutex_lock(&gsi->mutex);
|
|
setup_qps(gsi);
|
|
mutex_unlock(&gsi->mutex);
|
|
}
|