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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3b0d65969b
Add PSHUFB macros instead of repeating byte sequences, suggested by Ingo. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Acked-by: Ingo Molnar <mingo@elte.hu>
422 lines
10 KiB
C
422 lines
10 KiB
C
/*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* General FPU state handling cleanups
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* Gareth Hughes <gareth@valinux.com>, May 2000
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* x86-64 work by Andi Kleen 2002
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*/
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#ifndef _ASM_X86_I387_H
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#define _ASM_X86_I387_H
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/regset.h>
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#include <linux/hardirq.h>
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#include <asm/asm.h>
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#include <asm/processor.h>
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#include <asm/sigcontext.h>
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#include <asm/user.h>
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#include <asm/uaccess.h>
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#include <asm/xsave.h>
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extern unsigned int sig_xstate_size;
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extern void fpu_init(void);
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extern void mxcsr_feature_mask_init(void);
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extern int init_fpu(struct task_struct *child);
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extern asmlinkage void math_state_restore(void);
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extern void __math_state_restore(void);
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extern void init_thread_xstate(void);
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extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
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extern user_regset_active_fn fpregs_active, xfpregs_active;
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extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
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extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
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extern struct _fpx_sw_bytes fx_sw_reserved;
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#ifdef CONFIG_IA32_EMULATION
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extern unsigned int sig_xstate_ia32_size;
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extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
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struct _fpstate_ia32;
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struct _xstate_ia32;
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extern int save_i387_xstate_ia32(void __user *buf);
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extern int restore_i387_xstate_ia32(void __user *buf);
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#endif
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#define X87_FSW_ES (1 << 7) /* Exception Summary */
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#ifdef CONFIG_X86_64
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/* Ignore delayed exceptions from user space */
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static inline void tolerant_fwait(void)
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{
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asm volatile("1: fwait\n"
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"2:\n"
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_ASM_EXTABLE(1b, 2b));
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}
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static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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{
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int err;
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asm volatile("1: rex64/fxrstor (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: [err] "=r" (err)
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#if 0 /* See comment in fxsave() below. */
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: [fx] "r" (fx), "m" (*fx), "0" (0));
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#else
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: [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
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#endif
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return err;
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}
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/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
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is pending. Clear the x87 state here by setting it to fixed
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values. The kernel data segment can be sometimes 0 and sometimes
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new user value. Both should be ok.
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Use the PDA as safe address because it should be already in L1. */
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static inline void clear_fpu_state(struct task_struct *tsk)
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{
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struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
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struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
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/*
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* xsave header may indicate the init state of the FP.
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*/
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if ((task_thread_info(tsk)->status & TS_XSAVE) &&
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!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
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return;
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if (unlikely(fx->swd & X87_FSW_ES))
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asm volatile("fnclex");
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alternative_input(ASM_NOP8 ASM_NOP2,
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" emms\n" /* clear stack tags */
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" fildl %%gs:0", /* load to clear state */
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X86_FEATURE_FXSAVE_LEAK);
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}
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static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
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{
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int err;
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asm volatile("1: rex64/fxsave (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: [err] "=r" (err), "=m" (*fx)
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#if 0 /* See comment in fxsave() below. */
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: [fx] "r" (fx), "0" (0));
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#else
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: [fx] "cdaSDb" (fx), "0" (0));
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#endif
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if (unlikely(err) &&
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__clear_user(fx, sizeof(struct i387_fxsave_struct)))
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err = -EFAULT;
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/* No need to clear here because the caller clears USED_MATH */
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return err;
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}
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static inline void fxsave(struct task_struct *tsk)
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{
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/* Using "rex64; fxsave %0" is broken because, if the memory operand
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uses any extended registers for addressing, a second REX prefix
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will be generated (to the assembler, rex64 followed by semicolon
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is a separate instruction), and hence the 64-bitness is lost. */
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#if 0
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/* Using "fxsaveq %0" would be the ideal choice, but is only supported
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starting with gas 2.16. */
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__asm__ __volatile__("fxsaveq %0"
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: "=m" (tsk->thread.xstate->fxsave));
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#elif 0
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/* Using, as a workaround, the properly prefixed form below isn't
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accepted by any binutils version so far released, complaining that
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the same type of prefix is used twice if an extended register is
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needed for addressing (fix submitted to mainline 2005-11-21). */
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__asm__ __volatile__("rex64/fxsave %0"
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: "=m" (tsk->thread.xstate->fxsave));
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#else
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/* This, however, we can work around by forcing the compiler to select
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an addressing mode that doesn't require extended registers. */
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__asm__ __volatile__("rex64/fxsave (%1)"
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: "=m" (tsk->thread.xstate->fxsave)
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: "cdaSDb" (&tsk->thread.xstate->fxsave));
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#endif
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}
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static inline void __save_init_fpu(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_XSAVE)
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xsave(tsk);
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else
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fxsave(tsk);
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clear_fpu_state(tsk);
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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}
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#else /* CONFIG_X86_32 */
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#ifdef CONFIG_MATH_EMULATION
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extern void finit_task(struct task_struct *tsk);
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#else
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static inline void finit_task(struct task_struct *tsk)
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{
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}
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#endif
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static inline void tolerant_fwait(void)
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{
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asm volatile("fnclex ; fwait");
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}
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/* perform fxrstor iff the processor has extended states, otherwise frstor */
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static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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{
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/*
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* The "nop" is needed to make the instructions the same
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* length.
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*/
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alternative_input(
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"nop ; frstor %1",
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"fxrstor %1",
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X86_FEATURE_FXSR,
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"m" (*fx));
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return 0;
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}
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/* We need a safe address that is cheap to find and that is already
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in L1 during context switch. The best choices are unfortunately
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different for UP and SMP */
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#ifdef CONFIG_SMP
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#define safe_address (__per_cpu_offset[0])
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#else
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#define safe_address (kstat_cpu(0).cpustat.user)
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#endif
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/*
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* These must be called with preempt disabled
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*/
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static inline void __save_init_fpu(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_XSAVE) {
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struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
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struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
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xsave(tsk);
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/*
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* xsave header may indicate the init state of the FP.
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*/
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if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
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goto end;
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if (unlikely(fx->swd & X87_FSW_ES))
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asm volatile("fnclex");
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/*
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* we can do a simple return here or be paranoid :)
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*/
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goto clear_state;
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}
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/* Use more nops than strictly needed in case the compiler
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varies code */
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alternative_input(
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"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
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"fxsave %[fx]\n"
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"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
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X86_FEATURE_FXSR,
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[fx] "m" (tsk->thread.xstate->fxsave),
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[fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
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clear_state:
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/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
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is pending. Clear the x87 state here by setting it to fixed
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values. safe_address is a random variable that should be in L1 */
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alternative_input(
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GENERIC_NOP8 GENERIC_NOP2,
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"emms\n\t" /* clear stack tags */
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"fildl %[addr]", /* set F?P to defined value */
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X86_FEATURE_FXSAVE_LEAK,
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[addr] "m" (safe_address));
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end:
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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}
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#endif /* CONFIG_X86_64 */
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static inline int restore_fpu_checking(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_XSAVE)
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return xrstor_checking(&tsk->thread.xstate->xsave);
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else
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return fxrstor_checking(&tsk->thread.xstate->fxsave);
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}
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/*
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* Signal frame handlers...
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*/
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extern int save_i387_xstate(void __user *buf);
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extern int restore_i387_xstate(void __user *buf);
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static inline void __unlazy_fpu(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_USEDFPU) {
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__save_init_fpu(tsk);
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stts();
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} else
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tsk->fpu_counter = 0;
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}
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static inline void __clear_fpu(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_USEDFPU) {
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tolerant_fwait();
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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stts();
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}
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}
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static inline void kernel_fpu_begin(void)
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{
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struct thread_info *me = current_thread_info();
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preempt_disable();
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if (me->status & TS_USEDFPU)
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__save_init_fpu(me->task);
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else
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clts();
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}
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static inline void kernel_fpu_end(void)
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{
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stts();
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preempt_enable();
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}
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static inline bool irq_fpu_usable(void)
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{
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struct pt_regs *regs;
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return !in_interrupt() || !(regs = get_irq_regs()) || \
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user_mode(regs) || (read_cr0() & X86_CR0_TS);
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}
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/*
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* Some instructions like VIA's padlock instructions generate a spurious
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* DNA fault but don't modify SSE registers. And these instructions
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* get used from interrupt context as well. To prevent these kernel instructions
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* in interrupt context interacting wrongly with other user/kernel fpu usage, we
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* should use them only in the context of irq_ts_save/restore()
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*/
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static inline int irq_ts_save(void)
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{
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/*
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* If in process context and not atomic, we can take a spurious DNA fault.
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* Otherwise, doing clts() in process context requires disabling preemption
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* or some heavy lifting like kernel_fpu_begin()
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*/
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if (!in_atomic())
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return 0;
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if (read_cr0() & X86_CR0_TS) {
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clts();
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return 1;
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}
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return 0;
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}
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static inline void irq_ts_restore(int TS_state)
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{
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if (TS_state)
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stts();
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}
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#ifdef CONFIG_X86_64
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static inline void save_init_fpu(struct task_struct *tsk)
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{
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__save_init_fpu(tsk);
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stts();
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}
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#define unlazy_fpu __unlazy_fpu
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#define clear_fpu __clear_fpu
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#else /* CONFIG_X86_32 */
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/*
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* These disable preemption on their own and are safe
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*/
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static inline void save_init_fpu(struct task_struct *tsk)
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{
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preempt_disable();
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__save_init_fpu(tsk);
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stts();
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preempt_enable();
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}
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static inline void unlazy_fpu(struct task_struct *tsk)
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{
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preempt_disable();
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__unlazy_fpu(tsk);
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preempt_enable();
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}
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static inline void clear_fpu(struct task_struct *tsk)
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{
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preempt_disable();
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__clear_fpu(tsk);
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preempt_enable();
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}
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#endif /* CONFIG_X86_64 */
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/*
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* i387 state interaction
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*/
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static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
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{
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if (cpu_has_fxsr) {
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return tsk->thread.xstate->fxsave.cwd;
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} else {
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return (unsigned short)tsk->thread.xstate->fsave.cwd;
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}
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}
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static inline unsigned short get_fpu_swd(struct task_struct *tsk)
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{
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if (cpu_has_fxsr) {
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return tsk->thread.xstate->fxsave.swd;
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} else {
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return (unsigned short)tsk->thread.xstate->fsave.swd;
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}
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}
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static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
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{
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if (cpu_has_xmm) {
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return tsk->thread.xstate->fxsave.mxcsr;
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} else {
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return MXCSR_DEFAULT;
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}
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}
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#endif /* __ASSEMBLY__ */
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#define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
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#define PSHUFB_XMM5_XMM6 .byte 0x66, 0x0f, 0x38, 0x00, 0xf5
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#endif /* _ASM_X86_I387_H */
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