mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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66314223aa
Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
148 lines
3.3 KiB
Plaintext
148 lines
3.3 KiB
Plaintext
/*
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* Copyright (C) 2012 Altera <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/include/ "skeleton.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &gmac0;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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intc: intc@fffed000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xfffed000 0x1000>,
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<0xfffec100 0x100>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges;
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@ffe01000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffe01000 0x1000>;
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interrupts = <0 180 4>;
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};
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};
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gmac0: stmmac@ff700000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
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reg = <0xff700000 0x2000>;
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interrupts = <0 115 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
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phy-mode = "gmii";
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};
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L2: l2-cache@fffef000 {
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compatible = "arm,pl310-cache";
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reg = <0xfffef000 0x1000>;
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interrupts = <0 38 0x04>;
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cache-unified;
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cache-level = <2>;
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};
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/* Local timer */
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timer@fffec600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xfffec600 0x100>;
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interrupts = <1 13 0xf04>;
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};
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timer0: timer@ffc08000 {
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compatible = "snps,dw-apb-timer-sp";
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interrupts = <0 167 4>;
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clock-frequency = <200000000>;
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reg = <0xffc08000 0x1000>;
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};
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timer1: timer@ffc09000 {
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compatible = "snps,dw-apb-timer-sp";
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interrupts = <0 168 4>;
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clock-frequency = <200000000>;
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reg = <0xffc09000 0x1000>;
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};
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timer2: timer@ffd00000 {
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compatible = "snps,dw-apb-timer-osc";
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interrupts = <0 169 4>;
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clock-frequency = <200000000>;
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reg = <0xffd00000 0x1000>;
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};
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timer3: timer@ffd01000 {
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compatible = "snps,dw-apb-timer-osc";
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interrupts = <0 170 4>;
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clock-frequency = <200000000>;
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reg = <0xffd01000 0x1000>;
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};
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uart0: uart@ffc02000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc02000 0x1000>;
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clock-frequency = <7372800>;
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interrupts = <0 162 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart1: uart@ffc03000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc03000 0x1000>;
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clock-frequency = <7372800>;
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interrupts = <0 163 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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};
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};
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