mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 16:36:52 +07:00
a1ac490d0d
replaced macros:
BNA_MAC_IS_EQUAL -> ether_addr_equal
BNA_POWER_OF_2 -> is_power_of_2
BNA_TO_POWER_OF_2_HIGH -> roundup_pow_of_two
removed unused macros:
bfa_fsm_get_state
bfa_ioc_clr_stats
bfa_ioc_fetch_stats
bfa_ioc_get_alt_ioc_fwstate
bfa_ioc_isr_mode_set
bfa_ioc_maxfrsize
bfa_ioc_mbox_cmd_pending
bfa_ioc_ownership_reset
bfa_ioc_rx_bbcredit
bfa_ioc_state_disabled
bfa_sm_cmp_state
bfa_sm_get_state
bfa_sm_send_event
bfa_sm_set_state
bfa_sm_state_decl
BFA_STRING_32
BFI_ADAPTER_IS_{PROTO,TTV,UNSUPP)
BFI_IOC_ENDIAN_SIG
BNA_{C,RX,TX}Q_PAGE_INDEX_MAX
BNA_{C,RX,TX}Q_PAGE_INDEX_MAX_SHIFT
BNA_{C,RX,TX}Q_QPGE_PTR_GET
BNA_IOC_TIMER_FREQ
BNA_MESSAGE_SIZE
BNA_QE_INDX_2_PTR
BNA_QE_INDX_RANGE
BNA_Q_GET_{C,P}I
BNA_Q_{C,P}I_ADD
BNA_Q_FREE_COUNT
BNA_Q_IN_USE_COUNT
BNA_TO_POWER_OF_2
containing_rec
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
560 lines
15 KiB
C
560 lines
15 KiB
C
/*
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* Linux network driver for QLogic BR-series Converged Network Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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/*
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* Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
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* Copyright (c) 2014-2015 QLogic Corporation
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* All rights reserved
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* www.qlogic.com
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*/
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#ifndef __BFI_H__
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#define __BFI_H__
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#include "bfa_defs.h"
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/* BFI FW image type */
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#define BFI_FLASH_CHUNK_SZ 256 /*!< Flash chunk size */
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#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
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#define BFI_FLASH_IMAGE_SZ 0x100000
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/* Msg header common to all msgs */
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struct bfi_mhdr {
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u8 msg_class; /*!< @ref enum bfi_mclass */
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u8 msg_id; /*!< msg opcode with in the class */
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union {
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struct {
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u8 qid;
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u8 fn_lpu; /*!< msg destination */
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} __packed h2i;
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u16 i2htok; /*!< token in msgs to host */
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} __packed mtag;
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} __packed;
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#define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu))
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#define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1)
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#define bfi_mhdr_2_qid(_mh) ((_mh)->mtag.h2i.qid)
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#define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do { \
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(_mh).msg_class = (_mc); \
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(_mh).msg_id = (_op); \
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(_mh).mtag.h2i.fn_lpu = (_fn_lpu); \
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} while (0)
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#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
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(_mh).msg_class = (_mc); \
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(_mh).msg_id = (_op); \
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(_mh).mtag.i2htok = (_i2htok); \
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} while (0)
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/*
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* Message opcodes: 0-127 to firmware, 128-255 to host
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*/
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#define BFI_I2H_OPCODE_BASE 128
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#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
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/****************************************************************************
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*
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* Scatter Gather Element and Page definition
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*
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****************************************************************************
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*/
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/* DMA addresses */
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union bfi_addr_u {
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struct {
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u32 addr_lo;
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u32 addr_hi;
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} __packed a32;
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} __packed;
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/* Generic DMA addr-len pair. */
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struct bfi_alen {
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union bfi_addr_u al_addr; /* DMA addr of buffer */
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u32 al_len; /* length of buffer */
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} __packed;
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/*
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* Large Message structure - 128 Bytes size Msgs
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*/
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#define BFI_LMSG_SZ 128
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#define BFI_LMSG_PL_WSZ \
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((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4)
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/* Mailbox message structure */
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#define BFI_MBMSG_SZ 7
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struct bfi_mbmsg {
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struct bfi_mhdr mh;
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u32 pl[BFI_MBMSG_SZ];
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} __packed;
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/* Supported PCI function class codes (personality) */
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enum bfi_pcifn_class {
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BFI_PCIFN_CLASS_FC = 0x0c04,
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BFI_PCIFN_CLASS_ETH = 0x0200,
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};
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/* Message Classes */
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enum bfi_mclass {
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BFI_MC_IOC = 1, /*!< IO Controller (IOC) */
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BFI_MC_DIAG = 2, /*!< Diagnostic Msgs */
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BFI_MC_FLASH = 3, /*!< Flash message class */
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BFI_MC_CEE = 4, /*!< CEE */
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BFI_MC_FCPORT = 5, /*!< FC port */
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BFI_MC_IOCFC = 6, /*!< FC - IO Controller (IOC) */
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BFI_MC_LL = 7, /*!< Link Layer */
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BFI_MC_UF = 8, /*!< Unsolicited frame receive */
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BFI_MC_FCXP = 9, /*!< FC Transport */
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BFI_MC_LPS = 10, /*!< lport fc login services */
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BFI_MC_RPORT = 11, /*!< Remote port */
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BFI_MC_ITNIM = 12, /*!< I-T nexus (Initiator mode) */
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BFI_MC_IOIM_READ = 13, /*!< read IO (Initiator mode) */
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BFI_MC_IOIM_WRITE = 14, /*!< write IO (Initiator mode) */
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BFI_MC_IOIM_IO = 15, /*!< IO (Initiator mode) */
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BFI_MC_IOIM = 16, /*!< IO (Initiator mode) */
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BFI_MC_IOIM_IOCOM = 17, /*!< good IO completion */
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BFI_MC_TSKIM = 18, /*!< Initiator Task management */
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BFI_MC_SBOOT = 19, /*!< SAN boot services */
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BFI_MC_IPFC = 20, /*!< IP over FC Msgs */
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BFI_MC_PORT = 21, /*!< Physical port */
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BFI_MC_SFP = 22, /*!< SFP module */
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BFI_MC_MSGQ = 23, /*!< MSGQ */
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BFI_MC_ENET = 24, /*!< ENET commands/responses */
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BFI_MC_PHY = 25, /*!< External PHY message class */
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BFI_MC_NBOOT = 26, /*!< Network Boot */
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BFI_MC_TIO_READ = 27, /*!< read IO (Target mode) */
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BFI_MC_TIO_WRITE = 28, /*!< write IO (Target mode) */
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BFI_MC_TIO_DATA_XFERED = 29, /*!< ds transferred (target mode) */
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BFI_MC_TIO_IO = 30, /*!< IO (Target mode) */
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BFI_MC_TIO = 31, /*!< IO (target mode) */
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BFI_MC_MFG = 32, /*!< MFG/ASIC block commands */
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BFI_MC_EDMA = 33, /*!< EDMA copy commands */
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BFI_MC_MAX = 34
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};
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#define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */
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#define BFI_FWBOOT_ENV_OS 0
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/*----------------------------------------------------------------------
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* IOC
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*----------------------------------------------------------------------
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*/
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/* Different asic generations */
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enum bfi_asic_gen {
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BFI_ASIC_GEN_CB = 1,
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BFI_ASIC_GEN_CT = 2,
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BFI_ASIC_GEN_CT2 = 3,
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};
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enum bfi_asic_mode {
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BFI_ASIC_MODE_FC = 1, /* FC up to 8G speed */
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BFI_ASIC_MODE_FC16 = 2, /* FC up to 16G speed */
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BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */
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BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */
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};
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enum bfi_ioc_h2i_msgs {
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BFI_IOC_H2I_ENABLE_REQ = 1,
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BFI_IOC_H2I_DISABLE_REQ = 2,
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BFI_IOC_H2I_GETATTR_REQ = 3,
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BFI_IOC_H2I_DBG_SYNC = 4,
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BFI_IOC_H2I_DBG_DUMP = 5,
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};
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enum bfi_ioc_i2h_msgs {
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BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
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BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
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BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
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BFI_IOC_I2H_HBEAT = BFA_I2HM(4),
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};
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/* BFI_IOC_H2I_GETATTR_REQ message */
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struct bfi_ioc_getattr_req {
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struct bfi_mhdr mh;
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union bfi_addr_u attr_addr;
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} __packed;
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struct bfi_ioc_attr {
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u64 mfg_pwwn; /*!< Mfg port wwn */
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u64 mfg_nwwn; /*!< Mfg node wwn */
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u8 mfg_mac[ETH_ALEN]; /*!< Mfg mac */
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u8 port_mode; /* enum bfi_port_mode */
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u8 rsvd_a;
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u64 pwwn;
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u64 nwwn;
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u8 mac[ETH_ALEN]; /*!< PBC or Mfg mac */
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u16 rsvd_b;
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u8 fcoe_mac[ETH_ALEN];
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u16 rsvd_c;
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char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
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u8 pcie_gen;
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u8 pcie_lanes_orig;
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u8 pcie_lanes;
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u8 rx_bbcredit; /*!< receive buffer credits */
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u32 adapter_prop; /*!< adapter properties */
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u16 maxfrsize; /*!< max receive frame size */
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char asic_rev;
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u8 rsvd_d;
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char fw_version[BFA_VERSION_LEN];
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char optrom_version[BFA_VERSION_LEN];
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struct bfa_mfg_vpd vpd;
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u32 card_type; /*!< card type */
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} __packed;
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/* BFI_IOC_I2H_GETATTR_REPLY message */
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struct bfi_ioc_getattr_reply {
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struct bfi_mhdr mh; /*!< Common msg header */
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u8 status; /*!< cfg reply status */
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u8 rsvd[3];
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} __packed;
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/* Firmware memory page offsets */
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#define BFI_IOC_SMEM_PG0_CB (0x40)
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#define BFI_IOC_SMEM_PG0_CT (0x180)
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/* Firmware statistic offset */
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#define BFI_IOC_FWSTATS_OFF (0x6B40)
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#define BFI_IOC_FWSTATS_SZ (4096)
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/* Firmware trace offset */
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#define BFI_IOC_TRC_OFF (0x4b00)
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#define BFI_IOC_TRC_ENTS 256
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#define BFI_IOC_TRC_ENT_SZ 16
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#define BFI_IOC_TRC_HDR_SZ 32
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#define BFI_IOC_FW_SIGNATURE (0xbfadbfad)
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#define BFI_IOC_FW_INV_SIGN (0xdeaddead)
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#define BFI_IOC_MD5SUM_SZ 4
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struct bfi_ioc_fwver {
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#ifdef __BIG_ENDIAN
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u8 patch;
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u8 maint;
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u8 minor;
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u8 major;
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u8 rsvd[2];
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u8 build;
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u8 phase;
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#else
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u8 major;
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u8 minor;
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u8 maint;
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u8 patch;
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u8 phase;
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u8 build;
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u8 rsvd[2];
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#endif
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} __packed;
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struct bfi_ioc_image_hdr {
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u32 signature; /*!< constant signature */
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u8 asic_gen; /*!< asic generation */
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u8 asic_mode;
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u8 port0_mode; /*!< device mode for port 0 */
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u8 port1_mode; /*!< device mode for port 1 */
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u32 exec; /*!< exec vector */
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u32 bootenv; /*!< firmware boot env */
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u32 rsvd_b[2];
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struct bfi_ioc_fwver fwver;
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u32 md5sum[BFI_IOC_MD5SUM_SZ];
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} __packed;
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enum bfi_ioc_img_ver_cmp {
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BFI_IOC_IMG_VER_INCOMP,
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BFI_IOC_IMG_VER_OLD,
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BFI_IOC_IMG_VER_SAME,
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BFI_IOC_IMG_VER_BETTER
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};
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#define BFI_FWBOOT_DEVMODE_OFF 4
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#define BFI_FWBOOT_TYPE_OFF 8
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#define BFI_FWBOOT_ENV_OFF 12
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#define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
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(((u32)(__asic_gen)) << 24 | \
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((u32)(__asic_mode)) << 16 | \
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((u32)(__p0_mode)) << 8 | \
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((u32)(__p1_mode)))
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enum bfi_fwboot_type {
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BFI_FWBOOT_TYPE_NORMAL = 0,
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BFI_FWBOOT_TYPE_FLASH = 1,
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BFI_FWBOOT_TYPE_MEMTEST = 2,
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};
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enum bfi_port_mode {
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BFI_PORT_MODE_FC = 1,
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BFI_PORT_MODE_ETH = 2,
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};
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struct bfi_ioc_hbeat {
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struct bfi_mhdr mh; /*!< common msg header */
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u32 hb_count; /*!< current heart beat count */
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} __packed;
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/* IOC hardware/firmware state */
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enum bfi_ioc_state {
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BFI_IOC_UNINIT = 0, /*!< not initialized */
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BFI_IOC_INITING = 1, /*!< h/w is being initialized */
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BFI_IOC_HWINIT = 2, /*!< h/w is initialized */
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BFI_IOC_CFG = 3, /*!< IOC configuration in progress */
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BFI_IOC_OP = 4, /*!< IOC is operational */
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BFI_IOC_DISABLING = 5, /*!< IOC is being disabled */
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BFI_IOC_DISABLED = 6, /*!< IOC is disabled */
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BFI_IOC_CFG_DISABLED = 7, /*!< IOC is being disabled;transient */
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BFI_IOC_FAIL = 8, /*!< IOC heart-beat failure */
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BFI_IOC_MEMTEST = 9, /*!< IOC is doing memtest */
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};
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enum {
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BFI_ADAPTER_TYPE_FC = 0x01, /*!< FC adapters */
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BFI_ADAPTER_TYPE_MK = 0x0f0000, /*!< adapter type mask */
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BFI_ADAPTER_TYPE_SH = 16, /*!< adapter type shift */
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BFI_ADAPTER_NPORTS_MK = 0xff00, /*!< number of ports mask */
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BFI_ADAPTER_NPORTS_SH = 8, /*!< number of ports shift */
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BFI_ADAPTER_SPEED_MK = 0xff, /*!< adapter speed mask */
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BFI_ADAPTER_SPEED_SH = 0, /*!< adapter speed shift */
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BFI_ADAPTER_PROTO = 0x100000, /*!< prototype adapaters */
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BFI_ADAPTER_TTV = 0x200000, /*!< TTV debug capable */
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BFI_ADAPTER_UNSUPP = 0x400000, /*!< unknown adapter type */
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};
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#define BFI_ADAPTER_GETP(__prop, __adap_prop) \
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(((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \
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BFI_ADAPTER_ ## __prop ## _SH)
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#define BFI_ADAPTER_SETP(__prop, __val) \
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((__val) << BFI_ADAPTER_ ## __prop ## _SH)
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#define BFI_ADAPTER_IS_SPECIAL(__adap_type) \
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((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \
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BFI_ADAPTER_UNSUPP))
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/* BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages */
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struct bfi_ioc_ctrl_req {
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struct bfi_mhdr mh;
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u16 clscode;
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u16 rsvd;
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u32 tv_sec;
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} __packed;
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/* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages */
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struct bfi_ioc_ctrl_reply {
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struct bfi_mhdr mh; /*!< Common msg header */
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u8 status; /*!< enable/disable status */
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u8 port_mode; /*!< enum bfa_mode */
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u8 cap_bm; /*!< capability bit mask */
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u8 rsvd;
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} __packed;
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#define BFI_IOC_MSGSZ 8
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/* H2I Messages */
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union bfi_ioc_h2i_msg_u {
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struct bfi_mhdr mh;
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struct bfi_ioc_ctrl_req enable_req;
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struct bfi_ioc_ctrl_req disable_req;
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struct bfi_ioc_getattr_req getattr_req;
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u32 mboxmsg[BFI_IOC_MSGSZ];
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} __packed;
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/* I2H Messages */
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union bfi_ioc_i2h_msg_u {
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struct bfi_mhdr mh;
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struct bfi_ioc_ctrl_reply fw_event;
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u32 mboxmsg[BFI_IOC_MSGSZ];
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} __packed;
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/*----------------------------------------------------------------------
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* MSGQ
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*----------------------------------------------------------------------
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*/
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enum bfi_msgq_h2i_msgs {
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BFI_MSGQ_H2I_INIT_REQ = 1,
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BFI_MSGQ_H2I_DOORBELL_PI = 2,
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BFI_MSGQ_H2I_DOORBELL_CI = 3,
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BFI_MSGQ_H2I_CMDQ_COPY_RSP = 4,
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};
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enum bfi_msgq_i2h_msgs {
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BFI_MSGQ_I2H_INIT_RSP = BFA_I2HM(BFI_MSGQ_H2I_INIT_REQ),
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BFI_MSGQ_I2H_DOORBELL_PI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_PI),
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BFI_MSGQ_I2H_DOORBELL_CI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_CI),
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BFI_MSGQ_I2H_CMDQ_COPY_REQ = BFA_I2HM(BFI_MSGQ_H2I_CMDQ_COPY_RSP),
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};
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/* Messages(commands/responsed/AENS will have the following header */
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struct bfi_msgq_mhdr {
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u8 msg_class;
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u8 msg_id;
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u16 msg_token;
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u16 num_entries;
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u8 enet_id;
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u8 rsvd[1];
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} __packed;
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#define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \
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(_mh).msg_class = (_mc); \
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(_mh).msg_id = (_mid); \
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(_mh).msg_token = (_tok); \
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(_mh).enet_id = (_enet_id); \
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} while (0)
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/*
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* Mailbox for messaging interface
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*/
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#define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */
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|
#define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */
|
|
|
|
#define bfi_msgq_num_cmd_entries(_size) \
|
|
(((_size) + BFI_MSGQ_CMD_ENTRY_SIZE - 1) / BFI_MSGQ_CMD_ENTRY_SIZE)
|
|
|
|
struct bfi_msgq {
|
|
union bfi_addr_u addr;
|
|
u16 q_depth; /* Total num of entries in the queue */
|
|
u8 rsvd[2];
|
|
} __packed;
|
|
|
|
/* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
|
|
struct bfi_msgq_cfg_req {
|
|
struct bfi_mhdr mh;
|
|
struct bfi_msgq cmdq;
|
|
struct bfi_msgq rspq;
|
|
} __packed;
|
|
|
|
/* BFI_ENET_MSGQ_CFG_RSP */
|
|
struct bfi_msgq_cfg_rsp {
|
|
struct bfi_mhdr mh;
|
|
u8 cmd_status;
|
|
u8 rsvd[3];
|
|
} __packed;
|
|
|
|
/* BFI_MSGQ_H2I_DOORBELL */
|
|
struct bfi_msgq_h2i_db {
|
|
struct bfi_mhdr mh;
|
|
union {
|
|
u16 cmdq_pi;
|
|
u16 rspq_ci;
|
|
} __packed idx;
|
|
} __packed;
|
|
|
|
/* BFI_MSGQ_I2H_DOORBELL */
|
|
struct bfi_msgq_i2h_db {
|
|
struct bfi_mhdr mh;
|
|
union {
|
|
u16 rspq_pi;
|
|
u16 cmdq_ci;
|
|
} __packed idx;
|
|
} __packed;
|
|
|
|
#define BFI_CMD_COPY_SZ 28
|
|
|
|
/* BFI_MSGQ_H2I_CMD_COPY_RSP */
|
|
struct bfi_msgq_h2i_cmdq_copy_rsp {
|
|
struct bfi_mhdr mh;
|
|
u8 data[BFI_CMD_COPY_SZ];
|
|
} __packed;
|
|
|
|
/* BFI_MSGQ_I2H_CMD_COPY_REQ */
|
|
struct bfi_msgq_i2h_cmdq_copy_req {
|
|
struct bfi_mhdr mh;
|
|
u16 offset;
|
|
u16 len;
|
|
} __packed;
|
|
|
|
/*
|
|
* FLASH module specific
|
|
*/
|
|
enum bfi_flash_h2i_msgs {
|
|
BFI_FLASH_H2I_QUERY_REQ = 1,
|
|
BFI_FLASH_H2I_ERASE_REQ = 2,
|
|
BFI_FLASH_H2I_WRITE_REQ = 3,
|
|
BFI_FLASH_H2I_READ_REQ = 4,
|
|
BFI_FLASH_H2I_BOOT_VER_REQ = 5,
|
|
};
|
|
|
|
enum bfi_flash_i2h_msgs {
|
|
BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1),
|
|
BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2),
|
|
BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3),
|
|
BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4),
|
|
BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5),
|
|
BFI_FLASH_I2H_EVENT = BFA_I2HM(127),
|
|
};
|
|
|
|
/*
|
|
* Flash query request
|
|
*/
|
|
struct bfi_flash_query_req {
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
struct bfi_alen alen;
|
|
} __packed;
|
|
|
|
/*
|
|
* Flash write request
|
|
*/
|
|
struct bfi_flash_write_req {
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
struct bfi_alen alen;
|
|
u32 type; /* partition type */
|
|
u8 instance; /* partition instance */
|
|
u8 last;
|
|
u8 rsv[2];
|
|
u32 offset;
|
|
u32 length;
|
|
} __packed;
|
|
|
|
/*
|
|
* Flash read request
|
|
*/
|
|
struct bfi_flash_read_req {
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
u32 type; /* partition type */
|
|
u8 instance; /* partition instance */
|
|
u8 rsv[3];
|
|
u32 offset;
|
|
u32 length;
|
|
struct bfi_alen alen;
|
|
} __packed;
|
|
|
|
/*
|
|
* Flash query response
|
|
*/
|
|
struct bfi_flash_query_rsp {
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
u32 status;
|
|
} __packed;
|
|
|
|
/*
|
|
* Flash read response
|
|
*/
|
|
struct bfi_flash_read_rsp {
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
u32 type; /* partition type */
|
|
u8 instance; /* partition instance */
|
|
u8 rsv[3];
|
|
u32 status;
|
|
u32 length;
|
|
} __packed;
|
|
|
|
/*
|
|
* Flash write response
|
|
*/
|
|
struct bfi_flash_write_rsp {
|
|
struct bfi_mhdr mh; /* Common msg header */
|
|
u32 type; /* partition type */
|
|
u8 instance; /* partition instance */
|
|
u8 rsv[3];
|
|
u32 status;
|
|
u32 length;
|
|
} __packed;
|
|
|
|
#endif /* __BFI_H__ */
|