mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 22:31:08 +07:00
d2f5a7311b
Since we have nice macro IRQ_RETVAL() we would use it to convert a flag of handled interrupt from int to irqreturn_t. The rationale of doing this is: a) hence we implicitly mark hsu_dma_do_irq() as an auxiliary function that can't be used as interrupt handler directly, and b) to be in align with serial driver which is using serial8250_handle_irq() that returns plain int by design. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
501 lines
13 KiB
C
501 lines
13 KiB
C
/*
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* Core driver for the High Speed UART DMA
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*
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* Copyright (C) 2015 Intel Corporation
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* Partially based on the bits found in drivers/tty/serial/mfd.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* DMA channel allocation:
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* 1. Even number chans are used for DMA Read (UART TX), odd chans for DMA
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* Write (UART RX).
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* 2. 0/1 channel are assigned to port 0, 2/3 chan to port 1, 4/5 chan to
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* port 3, and so on.
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*/
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "hsu.h"
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#define HSU_DMA_BUSWIDTHS \
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BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
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BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_16_BYTES)
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static inline void hsu_chan_disable(struct hsu_dma_chan *hsuc)
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{
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hsu_chan_writel(hsuc, HSU_CH_CR, 0);
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}
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static inline void hsu_chan_enable(struct hsu_dma_chan *hsuc)
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{
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u32 cr = HSU_CH_CR_CHA;
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if (hsuc->direction == DMA_MEM_TO_DEV)
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cr &= ~HSU_CH_CR_CHD;
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else if (hsuc->direction == DMA_DEV_TO_MEM)
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cr |= HSU_CH_CR_CHD;
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hsu_chan_writel(hsuc, HSU_CH_CR, cr);
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}
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static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
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{
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struct dma_slave_config *config = &hsuc->config;
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struct hsu_dma_desc *desc = hsuc->desc;
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u32 bsr = 0, mtsr = 0; /* to shut the compiler up */
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u32 dcr = HSU_CH_DCR_CHSOE | HSU_CH_DCR_CHEI;
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unsigned int i, count;
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if (hsuc->direction == DMA_MEM_TO_DEV) {
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bsr = config->dst_maxburst;
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mtsr = config->src_addr_width;
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} else if (hsuc->direction == DMA_DEV_TO_MEM) {
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bsr = config->src_maxburst;
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mtsr = config->dst_addr_width;
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}
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hsu_chan_disable(hsuc);
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hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
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hsu_chan_writel(hsuc, HSU_CH_BSR, bsr);
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hsu_chan_writel(hsuc, HSU_CH_MTSR, mtsr);
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/* Set descriptors */
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count = desc->nents - desc->active;
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for (i = 0; i < count && i < HSU_DMA_CHAN_NR_DESC; i++) {
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hsu_chan_writel(hsuc, HSU_CH_DxSAR(i), desc->sg[i].addr);
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hsu_chan_writel(hsuc, HSU_CH_DxTSR(i), desc->sg[i].len);
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/* Prepare value for DCR */
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dcr |= HSU_CH_DCR_DESCA(i);
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dcr |= HSU_CH_DCR_CHTOI(i); /* timeout bit, see HSU Errata 1 */
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desc->active++;
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}
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/* Only for the last descriptor in the chain */
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dcr |= HSU_CH_DCR_CHSOD(count - 1);
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dcr |= HSU_CH_DCR_CHDI(count - 1);
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hsu_chan_writel(hsuc, HSU_CH_DCR, dcr);
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hsu_chan_enable(hsuc);
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}
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static void hsu_dma_stop_channel(struct hsu_dma_chan *hsuc)
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{
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hsu_chan_disable(hsuc);
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hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
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}
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static void hsu_dma_start_channel(struct hsu_dma_chan *hsuc)
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{
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hsu_dma_chan_start(hsuc);
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}
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static void hsu_dma_start_transfer(struct hsu_dma_chan *hsuc)
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{
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struct virt_dma_desc *vdesc;
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/* Get the next descriptor */
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vdesc = vchan_next_desc(&hsuc->vchan);
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if (!vdesc) {
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hsuc->desc = NULL;
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return;
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}
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list_del(&vdesc->node);
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hsuc->desc = to_hsu_dma_desc(vdesc);
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/* Start the channel with a new descriptor */
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hsu_dma_start_channel(hsuc);
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}
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/*
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* hsu_dma_get_status() - get DMA channel status
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* @chip: HSUART DMA chip
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* @nr: DMA channel number
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* @status: pointer for DMA Channel Status Register value
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*
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* Description:
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* The function reads and clears the DMA Channel Status Register, checks
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* if it was a timeout interrupt and returns a corresponding value.
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*
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* Caller should provide a valid pointer for the DMA Channel Status
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* Register value that will be returned in @status.
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*
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* Return:
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* 1 for DMA timeout status, 0 for other DMA status, or error code for
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* invalid parameters or no interrupt pending.
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*/
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int hsu_dma_get_status(struct hsu_dma_chip *chip, unsigned short nr,
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u32 *status)
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{
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struct hsu_dma_chan *hsuc;
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unsigned long flags;
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u32 sr;
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/* Sanity check */
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if (nr >= chip->hsu->nr_channels)
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return -EINVAL;
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hsuc = &chip->hsu->chan[nr];
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/*
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* No matter what situation, need read clear the IRQ status
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* There is a bug, see Errata 5, HSD 2900918
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*/
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spin_lock_irqsave(&hsuc->vchan.lock, flags);
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sr = hsu_chan_readl(hsuc, HSU_CH_SR);
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spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
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/* Check if any interrupt is pending */
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sr &= ~(HSU_CH_SR_DESCE_ANY | HSU_CH_SR_CDESC_ANY);
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if (!sr)
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return -EIO;
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/* Timeout IRQ, need wait some time, see Errata 2 */
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if (sr & HSU_CH_SR_DESCTO_ANY)
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udelay(2);
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/*
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* At this point, at least one of Descriptor Time Out, Channel Error
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* or Descriptor Done bits must be set. Clear the Descriptor Time Out
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* bits and if sr is still non-zero, it must be channel error or
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* descriptor done which are higher priority than timeout and handled
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* in hsu_dma_do_irq(). Else, it must be a timeout.
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*/
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sr &= ~HSU_CH_SR_DESCTO_ANY;
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*status = sr;
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return sr ? 0 : 1;
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}
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EXPORT_SYMBOL_GPL(hsu_dma_get_status);
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/*
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* hsu_dma_do_irq() - DMA interrupt handler
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* @chip: HSUART DMA chip
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* @nr: DMA channel number
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* @status: Channel Status Register value
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*
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* Description:
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* This function handles Channel Error and Descriptor Done interrupts.
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* This function should be called after determining that the DMA interrupt
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* is not a normal timeout interrupt, ie. hsu_dma_get_status() returned 0.
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*
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* Return:
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* 0 for invalid channel number, 1 otherwise.
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*/
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int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status)
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{
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struct hsu_dma_chan *hsuc;
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struct hsu_dma_desc *desc;
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unsigned long flags;
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/* Sanity check */
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if (nr >= chip->hsu->nr_channels)
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return 0;
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hsuc = &chip->hsu->chan[nr];
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spin_lock_irqsave(&hsuc->vchan.lock, flags);
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desc = hsuc->desc;
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if (desc) {
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if (status & HSU_CH_SR_CHE) {
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desc->status = DMA_ERROR;
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} else if (desc->active < desc->nents) {
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hsu_dma_start_channel(hsuc);
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} else {
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vchan_cookie_complete(&desc->vdesc);
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desc->status = DMA_COMPLETE;
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hsu_dma_start_transfer(hsuc);
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}
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}
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spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
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return 1;
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}
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EXPORT_SYMBOL_GPL(hsu_dma_do_irq);
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static struct hsu_dma_desc *hsu_dma_alloc_desc(unsigned int nents)
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{
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struct hsu_dma_desc *desc;
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desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
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if (!desc)
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return NULL;
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desc->sg = kcalloc(nents, sizeof(*desc->sg), GFP_NOWAIT);
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if (!desc->sg) {
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kfree(desc);
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return NULL;
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}
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return desc;
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}
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static void hsu_dma_desc_free(struct virt_dma_desc *vdesc)
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{
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struct hsu_dma_desc *desc = to_hsu_dma_desc(vdesc);
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kfree(desc->sg);
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kfree(desc);
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}
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static struct dma_async_tx_descriptor *hsu_dma_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
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struct hsu_dma_desc *desc;
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struct scatterlist *sg;
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unsigned int i;
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desc = hsu_dma_alloc_desc(sg_len);
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if (!desc)
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return NULL;
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for_each_sg(sgl, sg, sg_len, i) {
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desc->sg[i].addr = sg_dma_address(sg);
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desc->sg[i].len = sg_dma_len(sg);
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desc->length += sg_dma_len(sg);
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}
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desc->nents = sg_len;
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desc->direction = direction;
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/* desc->active = 0 by kzalloc */
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desc->status = DMA_IN_PROGRESS;
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return vchan_tx_prep(&hsuc->vchan, &desc->vdesc, flags);
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}
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static void hsu_dma_issue_pending(struct dma_chan *chan)
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{
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struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&hsuc->vchan.lock, flags);
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if (vchan_issue_pending(&hsuc->vchan) && !hsuc->desc)
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hsu_dma_start_transfer(hsuc);
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spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
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}
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static size_t hsu_dma_active_desc_size(struct hsu_dma_chan *hsuc)
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{
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struct hsu_dma_desc *desc = hsuc->desc;
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size_t bytes = 0;
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int i;
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for (i = desc->active; i < desc->nents; i++)
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bytes += desc->sg[i].len;
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i = HSU_DMA_CHAN_NR_DESC - 1;
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do {
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bytes += hsu_chan_readl(hsuc, HSU_CH_DxTSR(i));
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} while (--i >= 0);
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return bytes;
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}
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static enum dma_status hsu_dma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *state)
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{
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struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
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struct virt_dma_desc *vdesc;
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enum dma_status status;
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size_t bytes;
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unsigned long flags;
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status = dma_cookie_status(chan, cookie, state);
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if (status == DMA_COMPLETE)
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return status;
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spin_lock_irqsave(&hsuc->vchan.lock, flags);
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vdesc = vchan_find_desc(&hsuc->vchan, cookie);
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if (hsuc->desc && cookie == hsuc->desc->vdesc.tx.cookie) {
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bytes = hsu_dma_active_desc_size(hsuc);
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dma_set_residue(state, bytes);
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status = hsuc->desc->status;
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} else if (vdesc) {
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bytes = to_hsu_dma_desc(vdesc)->length;
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dma_set_residue(state, bytes);
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}
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spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
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return status;
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}
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static int hsu_dma_slave_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
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/* Check if chan will be configured for slave transfers */
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if (!is_slave_direction(config->direction))
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return -EINVAL;
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memcpy(&hsuc->config, config, sizeof(hsuc->config));
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return 0;
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}
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static int hsu_dma_pause(struct dma_chan *chan)
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{
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struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&hsuc->vchan.lock, flags);
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if (hsuc->desc && hsuc->desc->status == DMA_IN_PROGRESS) {
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hsu_chan_disable(hsuc);
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hsuc->desc->status = DMA_PAUSED;
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}
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spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
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return 0;
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}
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static int hsu_dma_resume(struct dma_chan *chan)
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{
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struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
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unsigned long flags;
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spin_lock_irqsave(&hsuc->vchan.lock, flags);
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if (hsuc->desc && hsuc->desc->status == DMA_PAUSED) {
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hsuc->desc->status = DMA_IN_PROGRESS;
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hsu_chan_enable(hsuc);
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}
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spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
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return 0;
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}
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static int hsu_dma_terminate_all(struct dma_chan *chan)
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{
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struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
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unsigned long flags;
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LIST_HEAD(head);
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spin_lock_irqsave(&hsuc->vchan.lock, flags);
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hsu_dma_stop_channel(hsuc);
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if (hsuc->desc) {
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hsu_dma_desc_free(&hsuc->desc->vdesc);
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hsuc->desc = NULL;
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}
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vchan_get_all_descriptors(&hsuc->vchan, &head);
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spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
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vchan_dma_desc_free_list(&hsuc->vchan, &head);
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return 0;
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}
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static void hsu_dma_free_chan_resources(struct dma_chan *chan)
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{
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vchan_free_chan_resources(to_virt_chan(chan));
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}
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int hsu_dma_probe(struct hsu_dma_chip *chip)
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{
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struct hsu_dma *hsu;
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void __iomem *addr = chip->regs + chip->offset;
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unsigned short i;
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int ret;
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hsu = devm_kzalloc(chip->dev, sizeof(*hsu), GFP_KERNEL);
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if (!hsu)
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return -ENOMEM;
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chip->hsu = hsu;
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/* Calculate nr_channels from the IO space length */
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hsu->nr_channels = (chip->length - chip->offset) / HSU_DMA_CHAN_LENGTH;
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hsu->chan = devm_kcalloc(chip->dev, hsu->nr_channels,
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sizeof(*hsu->chan), GFP_KERNEL);
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if (!hsu->chan)
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return -ENOMEM;
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INIT_LIST_HEAD(&hsu->dma.channels);
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for (i = 0; i < hsu->nr_channels; i++) {
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struct hsu_dma_chan *hsuc = &hsu->chan[i];
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hsuc->vchan.desc_free = hsu_dma_desc_free;
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vchan_init(&hsuc->vchan, &hsu->dma);
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hsuc->direction = (i & 0x1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
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hsuc->reg = addr + i * HSU_DMA_CHAN_LENGTH;
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}
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dma_cap_set(DMA_SLAVE, hsu->dma.cap_mask);
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dma_cap_set(DMA_PRIVATE, hsu->dma.cap_mask);
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hsu->dma.device_free_chan_resources = hsu_dma_free_chan_resources;
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hsu->dma.device_prep_slave_sg = hsu_dma_prep_slave_sg;
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hsu->dma.device_issue_pending = hsu_dma_issue_pending;
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hsu->dma.device_tx_status = hsu_dma_tx_status;
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hsu->dma.device_config = hsu_dma_slave_config;
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hsu->dma.device_pause = hsu_dma_pause;
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hsu->dma.device_resume = hsu_dma_resume;
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hsu->dma.device_terminate_all = hsu_dma_terminate_all;
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hsu->dma.src_addr_widths = HSU_DMA_BUSWIDTHS;
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hsu->dma.dst_addr_widths = HSU_DMA_BUSWIDTHS;
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hsu->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
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hsu->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
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hsu->dma.dev = chip->dev;
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dma_set_max_seg_size(hsu->dma.dev, HSU_CH_DxTSR_MASK);
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ret = dma_async_device_register(&hsu->dma);
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if (ret)
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return ret;
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dev_info(chip->dev, "Found HSU DMA, %d channels\n", hsu->nr_channels);
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return 0;
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}
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EXPORT_SYMBOL_GPL(hsu_dma_probe);
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int hsu_dma_remove(struct hsu_dma_chip *chip)
|
|
{
|
|
struct hsu_dma *hsu = chip->hsu;
|
|
unsigned short i;
|
|
|
|
dma_async_device_unregister(&hsu->dma);
|
|
|
|
for (i = 0; i < hsu->nr_channels; i++) {
|
|
struct hsu_dma_chan *hsuc = &hsu->chan[i];
|
|
|
|
tasklet_kill(&hsuc->vchan.task);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hsu_dma_remove);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("High Speed UART DMA core driver");
|
|
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|