mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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174122c39c
The SHA256 digest is an array of 8 32-bit quantities, so we should refer
to them as such in order for this code to work correctly when built for
big endian. So replace 16 byte scalar loads and stores with 4x32 vector
ones where appropriate.
Fixes: 6ba6c74dfc ("arm64/crypto: SHA-224/SHA-256 using ARMv8 Crypto Extensions")
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
154 lines
3.8 KiB
ArmAsm
154 lines
3.8 KiB
ArmAsm
/*
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* sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
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*
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* Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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.arch armv8-a+crypto
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dga .req q20
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dgav .req v20
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dgb .req q21
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dgbv .req v21
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t0 .req v22
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t1 .req v23
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dg0q .req q24
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dg0v .req v24
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dg1q .req q25
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dg1v .req v25
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dg2q .req q26
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dg2v .req v26
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.macro add_only, ev, rc, s0
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mov dg2v.16b, dg0v.16b
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.ifeq \ev
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add t1.4s, v\s0\().4s, \rc\().4s
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sha256h dg0q, dg1q, t0.4s
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sha256h2 dg1q, dg2q, t0.4s
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.else
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.ifnb \s0
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add t0.4s, v\s0\().4s, \rc\().4s
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.endif
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sha256h dg0q, dg1q, t1.4s
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sha256h2 dg1q, dg2q, t1.4s
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.endif
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.endm
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.macro add_update, ev, rc, s0, s1, s2, s3
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sha256su0 v\s0\().4s, v\s1\().4s
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add_only \ev, \rc, \s1
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sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
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.endm
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/*
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* The SHA-256 round constants
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*/
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.align 4
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.Lsha2_rcon:
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.word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
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.word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
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.word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
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.word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
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.word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
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.word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
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.word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
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.word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
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.word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
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.word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
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.word 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
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.word 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
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.word 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
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.word 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
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.word 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
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.word 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
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/*
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* void sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src,
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* int blocks)
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*/
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ENTRY(sha2_ce_transform)
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/* load round constants */
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adr x8, .Lsha2_rcon
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ld1 { v0.4s- v3.4s}, [x8], #64
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ld1 { v4.4s- v7.4s}, [x8], #64
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ld1 { v8.4s-v11.4s}, [x8], #64
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ld1 {v12.4s-v15.4s}, [x8]
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/* load state */
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ld1 {dgav.4s, dgbv.4s}, [x0]
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/* load sha256_ce_state::finalize */
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ldr w4, [x0, #:lo12:sha256_ce_offsetof_finalize]
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/* load input */
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0: ld1 {v16.4s-v19.4s}, [x1], #64
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sub w2, w2, #1
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CPU_LE( rev32 v16.16b, v16.16b )
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CPU_LE( rev32 v17.16b, v17.16b )
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CPU_LE( rev32 v18.16b, v18.16b )
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CPU_LE( rev32 v19.16b, v19.16b )
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1: add t0.4s, v16.4s, v0.4s
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mov dg0v.16b, dgav.16b
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mov dg1v.16b, dgbv.16b
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add_update 0, v1, 16, 17, 18, 19
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add_update 1, v2, 17, 18, 19, 16
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add_update 0, v3, 18, 19, 16, 17
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add_update 1, v4, 19, 16, 17, 18
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add_update 0, v5, 16, 17, 18, 19
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add_update 1, v6, 17, 18, 19, 16
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add_update 0, v7, 18, 19, 16, 17
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add_update 1, v8, 19, 16, 17, 18
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add_update 0, v9, 16, 17, 18, 19
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add_update 1, v10, 17, 18, 19, 16
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add_update 0, v11, 18, 19, 16, 17
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add_update 1, v12, 19, 16, 17, 18
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add_only 0, v13, 17
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add_only 1, v14, 18
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add_only 0, v15, 19
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add_only 1
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/* update state */
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add dgav.4s, dgav.4s, dg0v.4s
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add dgbv.4s, dgbv.4s, dg1v.4s
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/* handled all input blocks? */
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cbnz w2, 0b
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/*
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* Final block: add padding and total bit count.
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* Skip if the input size was not a round multiple of the block size,
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* the padding is handled by the C code in that case.
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*/
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cbz x4, 3f
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ldr x4, [x0, #:lo12:sha256_ce_offsetof_count]
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movi v17.2d, #0
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mov x8, #0x80000000
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movi v18.2d, #0
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ror x7, x4, #29 // ror(lsl(x4, 3), 32)
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fmov d16, x8
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mov x4, #0
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mov v19.d[0], xzr
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mov v19.d[1], x7
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b 1b
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/* store new state */
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3: st1 {dgav.4s, dgbv.4s}, [x0]
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ret
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ENDPROC(sha2_ce_transform)
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