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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dee39247dc
We're now ready to map our vectors in weird and wonderful locations. On enabling ARM64_HARDEN_EL2_VECTORS, a vector slot gets allocated if this hasn't been already done via ARM64_HARDEN_BRANCH_PREDICTOR and gets mapped outside of the normal RAM region, next to the idmap. That way, being able to obtain VBAR_EL2 doesn't reveal the mapping of the rest of the hypervisor code. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
100 lines
2.8 KiB
C
100 lines
2.8 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_MMU_H
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#define __ASM_MMU_H
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#define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */
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#define USER_ASID_BIT 48
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#define USER_ASID_FLAG (UL(1) << USER_ASID_BIT)
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#define TTBR_ASID_MASK (UL(0xffff) << 48)
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#define BP_HARDEN_EL2_SLOTS 4
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#ifndef __ASSEMBLY__
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typedef struct {
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atomic64_t id;
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void *vdso;
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unsigned long flags;
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} mm_context_t;
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/*
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* This macro is only used by the TLBI code, which cannot race with an
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* ASID change and therefore doesn't need to reload the counter using
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* atomic64_read.
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*/
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#define ASID(mm) ((mm)->context.id.counter & 0xffff)
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static inline bool arm64_kernel_unmapped_at_el0(void)
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{
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return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) &&
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cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0);
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}
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typedef void (*bp_hardening_cb_t)(void);
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struct bp_hardening_data {
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int hyp_vectors_slot;
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bp_hardening_cb_t fn;
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};
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#if (defined(CONFIG_HARDEN_BRANCH_PREDICTOR) || \
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defined(CONFIG_HARDEN_EL2_VECTORS))
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extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[];
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extern atomic_t arm64_el2_vector_last_slot;
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR || CONFIG_HARDEN_EL2_VECTORS */
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
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{
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return this_cpu_ptr(&bp_hardening_data);
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}
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static inline void arm64_apply_bp_hardening(void)
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{
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struct bp_hardening_data *d;
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if (!cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR))
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return;
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d = arm64_get_bp_hardening_data();
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if (d->fn)
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d->fn();
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}
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#else
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static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
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{
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return NULL;
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}
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static inline void arm64_apply_bp_hardening(void) { }
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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extern void paging_init(void);
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extern void bootmem_init(void);
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extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
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extern void init_mem_pgprot(void);
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extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
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unsigned long virt, phys_addr_t size,
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pgprot_t prot, bool page_mappings_only);
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extern void *fixmap_remap_fdt(phys_addr_t dt_phys);
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extern void mark_linear_text_alias_ro(void);
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#endif /* !__ASSEMBLY__ */
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#endif
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