Isabel Zhang 15add0c2fe drm/amd/display: Add initialitions for PLL2 clock source ... [Why] Starting from 14nm, the PLL is built into the PHY and the PLL is mapped to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not initialized. This causes DP to HDMI dongle to not light up the display. [How] Initializations added for PLL2 when creating resources. Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-06 15:04:38 -05:00
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acp	drm/amdgpu: fix license on Kconfig and Makefiles	2019-12-11 15:22:08 -05:00
amdgpu	drm/amdgpu: move xgmi init/fini to xgmi_add/remove_device call (v2)	2020-02-06 15:04:36 -05:00
amdkfd	drm/amdkfd: Fix a bug in SDMA RLC queue counting under HWS mode	2020-02-04 10:32:41 -05:00
display	drm/amd/display: Add initialitions for PLL2 clock source	2020-02-06 15:04:38 -05:00
include	drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus	2020-01-30 17:15:27 -05:00
powerplay	drm/amdgpu: update default voltage for boot od table for navi1x	2020-02-04 23:30:38 -05:00