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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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049359d655
This patch adds support for AMCC ppc4xx security device driver. This is the initial release that includes the driver framework with AES and SHA1 algorithms support. The remaining algorithms will be released in the near future. Signed-off-by: James Hsiao <jhsiao@amcc.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
244 lines
5.6 KiB
C
244 lines
5.6 KiB
C
/**
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* AMCC SoC PPC4xx Crypto Driver
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*
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* Copyright (c) 2008 Applied Micro Circuits Corporation.
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* All rights reserved. James Hsiao <jhsiao@amcc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This file defines the security context
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* assoicate format.
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*/
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#ifndef __CRYPTO4XX_SA_H__
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#define __CRYPTO4XX_SA_H__
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#define AES_IV_SIZE 16
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/**
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* Contents of Dynamic Security Association (SA) with all possible fields
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*/
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union dynamic_sa_contents {
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struct {
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u32 arc4_state_ptr:1;
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u32 arc4_ij_ptr:1;
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u32 state_ptr:1;
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u32 iv3:1;
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u32 iv2:1;
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u32 iv1:1;
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u32 iv0:1;
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u32 seq_num_mask3:1;
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u32 seq_num_mask2:1;
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u32 seq_num_mask1:1;
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u32 seq_num_mask0:1;
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u32 seq_num1:1;
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u32 seq_num0:1;
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u32 spi:1;
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u32 outer_size:5;
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u32 inner_size:5;
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u32 key_size:4;
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u32 cmd_size:4;
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} bf;
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u32 w;
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} __attribute__((packed));
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#define DIR_OUTBOUND 0
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#define DIR_INBOUND 1
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#define SA_OP_GROUP_BASIC 0
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#define SA_OPCODE_ENCRYPT 0
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#define SA_OPCODE_DECRYPT 0
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#define SA_OPCODE_HASH 3
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#define SA_CIPHER_ALG_DES 0
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#define SA_CIPHER_ALG_3DES 1
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#define SA_CIPHER_ALG_ARC4 2
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#define SA_CIPHER_ALG_AES 3
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#define SA_CIPHER_ALG_KASUMI 4
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#define SA_CIPHER_ALG_NULL 15
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#define SA_HASH_ALG_MD5 0
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#define SA_HASH_ALG_SHA1 1
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#define SA_HASH_ALG_NULL 15
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#define SA_HASH_ALG_SHA1_DIGEST_SIZE 20
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#define SA_LOAD_HASH_FROM_SA 0
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#define SA_LOAD_HASH_FROM_STATE 2
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#define SA_NOT_LOAD_HASH 3
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#define SA_LOAD_IV_FROM_SA 0
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#define SA_LOAD_IV_FROM_INPUT 1
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#define SA_LOAD_IV_FROM_STATE 2
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#define SA_LOAD_IV_GEN_IV 3
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#define SA_PAD_TYPE_CONSTANT 2
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#define SA_PAD_TYPE_ZERO 3
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#define SA_PAD_TYPE_TLS 5
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#define SA_PAD_TYPE_DTLS 5
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#define SA_NOT_SAVE_HASH 0
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#define SA_SAVE_HASH 1
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#define SA_NOT_SAVE_IV 0
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#define SA_SAVE_IV 1
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#define SA_HEADER_PROC 1
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#define SA_NO_HEADER_PROC 0
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union sa_command_0 {
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struct {
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u32 scatter:1;
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u32 gather:1;
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u32 save_hash_state:1;
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u32 save_iv:1;
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u32 load_hash_state:2;
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u32 load_iv:2;
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u32 digest_len:4;
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u32 hdr_proc:1;
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u32 extend_pad:1;
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u32 stream_cipher_pad:1;
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u32 rsv:1;
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u32 hash_alg:4;
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u32 cipher_alg:4;
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u32 pad_type:2;
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u32 op_group:2;
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u32 dir:1;
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u32 opcode:3;
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} bf;
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u32 w;
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} __attribute__((packed));
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#define CRYPTO_MODE_ECB 0
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#define CRYPTO_MODE_CBC 1
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#define CRYPTO_FEEDBACK_MODE_NO_FB 0
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#define CRYPTO_FEEDBACK_MODE_64BIT_OFB 0
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#define CRYPTO_FEEDBACK_MODE_8BIT_CFB 1
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#define CRYPTO_FEEDBACK_MODE_1BIT_CFB 2
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#define CRYPTO_FEEDBACK_MODE_128BIT_CFB 3
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#define SA_AES_KEY_LEN_128 2
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#define SA_AES_KEY_LEN_192 3
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#define SA_AES_KEY_LEN_256 4
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#define SA_REV2 1
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/**
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* The follow defines bits sa_command_1
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* In Basic hash mode this bit define simple hash or hmac.
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* In IPsec mode, this bit define muting control.
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*/
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#define SA_HASH_MODE_HASH 0
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#define SA_HASH_MODE_HMAC 1
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#define SA_MC_ENABLE 0
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#define SA_MC_DISABLE 1
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#define SA_NOT_COPY_HDR 0
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#define SA_COPY_HDR 1
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#define SA_NOT_COPY_PAD 0
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#define SA_COPY_PAD 1
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#define SA_NOT_COPY_PAYLOAD 0
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#define SA_COPY_PAYLOAD 1
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#define SA_EXTENDED_SN_OFF 0
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#define SA_EXTENDED_SN_ON 1
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#define SA_SEQ_MASK_OFF 0
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#define SA_SEQ_MASK_ON 1
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union sa_command_1 {
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struct {
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u32 crypto_mode31:1;
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u32 save_arc4_state:1;
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u32 arc4_stateful:1;
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u32 key_len:5;
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u32 hash_crypto_offset:8;
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u32 sa_rev:2;
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u32 byte_offset:1;
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u32 hmac_muting:1;
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u32 feedback_mode:2;
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u32 crypto_mode9_8:2;
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u32 extended_seq_num:1;
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u32 seq_num_mask:1;
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u32 mutable_bit_proc:1;
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u32 ip_version:1;
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u32 copy_pad:1;
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u32 copy_payload:1;
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u32 copy_hdr:1;
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u32 rsv1:1;
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} bf;
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u32 w;
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} __attribute__((packed));
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struct dynamic_sa_ctl {
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u32 sa_contents;
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union sa_command_0 sa_command_0;
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union sa_command_1 sa_command_1;
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} __attribute__((packed));
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/**
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* State Record for Security Association (SA)
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*/
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struct sa_state_record {
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u32 save_iv[4];
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u32 save_hash_byte_cnt[2];
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u32 save_digest[16];
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} __attribute__((packed));
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/**
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* Security Association (SA) for AES128
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*
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*/
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struct dynamic_sa_aes128 {
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struct dynamic_sa_ctl ctrl;
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u32 key[4];
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u32 iv[4]; /* for CBC, OFC, and CFB mode */
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u32 state_ptr;
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u32 reserved;
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} __attribute__((packed));
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#define SA_AES128_LEN (sizeof(struct dynamic_sa_aes128)/4)
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#define SA_AES128_CONTENTS 0x3e000042
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/*
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* Security Association (SA) for AES192
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*/
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struct dynamic_sa_aes192 {
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struct dynamic_sa_ctl ctrl;
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u32 key[6];
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u32 iv[4]; /* for CBC, OFC, and CFB mode */
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u32 state_ptr;
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u32 reserved;
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} __attribute__((packed));
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#define SA_AES192_LEN (sizeof(struct dynamic_sa_aes192)/4)
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#define SA_AES192_CONTENTS 0x3e000062
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/**
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* Security Association (SA) for AES256
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*/
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struct dynamic_sa_aes256 {
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struct dynamic_sa_ctl ctrl;
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u32 key[8];
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u32 iv[4]; /* for CBC, OFC, and CFB mode */
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u32 state_ptr;
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u32 reserved;
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} __attribute__((packed));
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#define SA_AES256_LEN (sizeof(struct dynamic_sa_aes256)/4)
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#define SA_AES256_CONTENTS 0x3e000082
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#define SA_AES_CONTENTS 0x3e000002
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/**
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* Security Association (SA) for HASH160: HMAC-SHA1
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*/
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struct dynamic_sa_hash160 {
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struct dynamic_sa_ctl ctrl;
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u32 inner_digest[5];
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u32 outer_digest[5];
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u32 state_ptr;
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u32 reserved;
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} __attribute__((packed));
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#define SA_HASH160_LEN (sizeof(struct dynamic_sa_hash160)/4)
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#define SA_HASH160_CONTENTS 0x2000a502
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#endif
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