Imre Deak 8cba903992 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock ... commit 0e2497e334de42dbaaee8e325241b5b5b34ede7e upstream. Apply Display WA #22010492432 for combo PHY PLLs too. This should fix a problem where the PLL output frequency is slightly off with the current PLL fractional divider value. I haven't seen an actual case where this causes a problem, but let's follow the spec. It's also needed on some EHL platforms, but for that we also need a way to distinguish the affected EHL SKUs, so I leave that for a follow-up. v2: - Apply the WA at one place when calculating the PLL dividers from the frequency and the frequency from the dividers for all the combo PLL use cases (DP, HDMI, TBT). (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201003001846.1271151-6-imre.deak@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2021-01-09 13:46:23 +01:00
..
drm	drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock	2021-01-09 13:46:23 +01:00
host1x	drm next for 5.10-rc1	2020-10-15 10:46:16 -07:00
ipu-v3	gpu: ipu-v3: remove unused functions	2020-10-26 10:42:38 +01:00
trace
vga
Makefile