mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 07:16:15 +07:00
d8f2be936c
Apart from the already enabled Designware HDMI port, the Utilite Pro
has a second display pipeline which has the following shape:
IPU1 DI0 --> Parallel display --> tfp410 rgb24 to DVI encoder
--> HDMI connector.
Enable support for it.
In addition, since this pipeline is hardwired to IPU1, sever the link
between IPU1 and the SoC-internal Designware HDMI encoder forcing the
latter to be connected to IPU2 instead of IPU1. Otherwise, it is not
possible to drive both displays at high resolution due to the bandwidth
limitations of a single IPU.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
342 lines
8.5 KiB
Plaintext
342 lines
8.5 KiB
Plaintext
/*
|
|
* Copyright 2013 CompuLab Ltd.
|
|
* Copyright 2016 Christopher Spinrath
|
|
*
|
|
* Based on the devicetree distributed with the vendor kernel for the
|
|
* Utilite Pro:
|
|
* Copyright 2013 CompuLab Ltd.
|
|
* Author: Valentin Raevsky <valentin@compulab.co.il>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This file is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <dt-bindings/input/input.h>
|
|
#include "imx6q-cm-fx6.dts"
|
|
|
|
/ {
|
|
model = "CompuLab Utilite Pro";
|
|
compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q";
|
|
|
|
aliases {
|
|
ethernet1 = ð1;
|
|
rtc0 = &em3027;
|
|
rtc1 = &snvs_rtc;
|
|
};
|
|
|
|
encoder {
|
|
compatible = "ti,tfp410";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
tfp410_in: endpoint {
|
|
remote-endpoint = <¶llel_display_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
tfp410_out: endpoint {
|
|
remote-endpoint = <&hdmi_connector_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
gpio-keys {
|
|
compatible = "gpio-keys";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_gpio_keys>;
|
|
|
|
power {
|
|
label = "Power Button";
|
|
gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_POWER>;
|
|
wakeup-source;
|
|
};
|
|
};
|
|
|
|
hdmi-connector {
|
|
compatible = "hdmi-connector";
|
|
|
|
type = "a";
|
|
ddc-i2c-bus = <&i2c_dvi_ddc>;
|
|
|
|
port {
|
|
hdmi_connector_in: endpoint {
|
|
remote-endpoint = <&tfp410_out>;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2cmux {
|
|
compatible = "i2c-mux-gpio";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1mux>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
|
|
i2c-parent = <&i2c1>;
|
|
|
|
i2c@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
eeprom@50 {
|
|
compatible = "at24,24c02";
|
|
reg = <0x50>;
|
|
pagesize = <16>;
|
|
};
|
|
|
|
em3027: rtc@56 {
|
|
compatible = "emmicro,em3027";
|
|
reg = <0x56>;
|
|
};
|
|
};
|
|
|
|
i2c_dvi_ddc: i2c@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
parallel-display {
|
|
compatible = "fsl,imx-parallel-display";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_ipu1>;
|
|
|
|
interface-pix-fmt = "rgb24";
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
parallel_display_in: endpoint {
|
|
remote-endpoint = <&ipu1_di0_disp0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
parallel_display_out: endpoint {
|
|
remote-endpoint = <&tfp410_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* A single IPU is not able to drive both display interfaces available on the
|
|
* Utilite Pro at high resolution due to its bandwidth limitation. Since the
|
|
* tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the
|
|
* SoC-internal Designware HDMI encoder forcing the latter to be connected to
|
|
* IPU2 instead of IPU1.
|
|
*/
|
|
/delete-node/&ipu1_di0_hdmi;
|
|
/delete-node/&hdmi_mux_0;
|
|
/delete-node/&ipu1_di1_hdmi;
|
|
/delete-node/&hdmi_mux_1;
|
|
|
|
&hdmi {
|
|
ddc-i2c-bus = <&i2c2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_gpio_keys: gpio_keysgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
|
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1mux: i2c1muxgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
|
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_ipu1: ipu1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
|
|
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
|
|
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
|
|
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
|
|
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
|
|
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
|
|
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
|
|
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
|
|
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
|
|
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
|
|
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
|
|
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
|
|
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
|
|
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
|
|
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
|
|
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
|
|
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
|
|
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
|
|
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
|
|
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
|
|
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
|
|
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
|
|
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
|
|
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
|
|
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
|
|
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
|
|
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
|
|
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
|
|
>;
|
|
};
|
|
};
|
|
|
|
&ipu1_di0_disp0 {
|
|
remote-endpoint = <¶llel_display_in>;
|
|
};
|
|
|
|
&pcie {
|
|
pcie@0,0 {
|
|
reg = <0x000000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
/* non-removable i211 ethernet card */
|
|
eth1: intel,i211@pcie0,0 {
|
|
reg = <0x010000 0 0 0 0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&uart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
uart-has-rtscts;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc3 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
no-1-8-v;
|
|
broken-cd;
|
|
keep-power-in-suspend;
|
|
status = "okay";
|
|
};
|