mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7958e54149
Some of the metrics use an incorrect syntax for specifying the cmask for an event. Convert to perf syntax so that they can be resolved. Fixes metrics on Broadwell, SandyBridge. Signed-off-by: Andi Kleen <ak@linux.intel.com> Link: http://lkml.kernel.org/n/tip-3k3fkfj8obek9dkmryyrqzhu@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
165 lines
7.4 KiB
JSON
165 lines
7.4 KiB
JSON
[
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{
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"BriefDescription": "Instructions Per Cycle (per logical thread)",
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"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
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"MetricGroup": "TopDownL1",
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"MetricName": "IPC"
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},
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{
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"BriefDescription": "Uops Per Instruction",
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"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
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"MetricGroup": "Pipeline",
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"MetricName": "UPI"
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},
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{
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"BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely consumed by program instructions",
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"MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )",
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"MetricGroup": "Frontend",
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"MetricName": "IFetch_Line_Utilization"
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},
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{
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"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache)",
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"MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )",
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"MetricGroup": "DSB; Frontend_Bandwidth",
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"MetricName": "DSB_Coverage"
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},
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{
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"BriefDescription": "Cycles Per Instruction (threaded)",
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"MetricExpr": "1 / (INST_RETIRED.ANY / cycles)",
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"MetricGroup": "Pipeline;Summary",
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"MetricName": "CPI"
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},
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{
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"BriefDescription": "Per-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTune.",
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"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
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"MetricGroup": "Summary",
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"MetricName": "CLKS"
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},
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{
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"BriefDescription": "Total issue-pipeline slots",
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"MetricExpr": "4*(( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles)",
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"MetricGroup": "TopDownL1",
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"MetricName": "SLOTS"
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},
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{
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"BriefDescription": "Total number of retired Instructions",
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"MetricExpr": "INST_RETIRED.ANY",
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"MetricGroup": "Summary",
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"MetricName": "Instructions"
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},
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{
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"BriefDescription": "Instructions Per Cycle (per physical core)",
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"MetricExpr": "INST_RETIRED.ANY / (( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles)",
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"MetricGroup": "SMT",
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"MetricName": "CoreIPC"
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},
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{
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"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
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"MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
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"MetricGroup": "Pipeline;Ports_Utilization",
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"MetricName": "ILP"
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},
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{
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"BriefDescription": "Average Branch Address Clear Cost (fraction of cycles)",
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"MetricExpr": "2* (( RS_EVENTS.EMPTY_CYCLES - ICACHE.IFDATA_STALL - (( 14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7* ITLB_MISSES.WALK_COMPLETED )) ) / RS_EVENTS.EMPTY_END)",
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"MetricGroup": "Unknown_Branches",
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"MetricName": "BAClear_Cost"
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},
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{
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"BriefDescription": "Core actual clocks when any thread is active on the physical core",
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"MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD",
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"MetricGroup": "SMT",
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"MetricName": "CORE_CLKS"
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},
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{
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"BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads",
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"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
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"MetricGroup": "Memory_Bound;Memory_Lat",
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"MetricName": "Load_Miss_Real_Latency"
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},
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{
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"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss)",
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"MetricExpr": "L1D_PEND_MISS.PENDING / (( cpu@l1d_pend_miss.pending_cycles\\,any\\=1@ / 2) if #SMT_on else L1D_PEND_MISS.PENDING_CYCLES)",
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"MetricGroup": "Memory_Bound;Memory_BW",
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"MetricName": "MLP"
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},
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{
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"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
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"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7*(DTLB_STORE_MISSES.WALK_COMPLETED+DTLB_LOAD_MISSES.WALK_COMPLETED+ITLB_MISSES.WALK_COMPLETED)) / (( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles)",
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"MetricGroup": "TLB",
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"MetricName": "Page_Walks_Utilization"
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},
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{
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"BriefDescription": "Average CPU Utilization",
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"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
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"MetricGroup": "Summary",
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"MetricName": "CPU_Utilization"
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},
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{
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"BriefDescription": "Giga Floating Point Operations Per Second",
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"MetricExpr": "(( 1*( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2* FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4*( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8* FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / 1000000000 / duration_time",
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"MetricGroup": "FLOPS;Summary",
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"MetricName": "GFLOPs"
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},
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{
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"BriefDescription": "Average Frequency Utilization relative nominal frequency",
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"MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC",
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"MetricGroup": "Power",
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"MetricName": "Turbo_Utilization"
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},
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{
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"BriefDescription": "Fraction of cycles where both hardware threads were active",
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"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
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"MetricGroup": "SMT;Summary",
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"MetricName": "SMT_2T_Utilization"
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},
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{
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"BriefDescription": "Fraction of cycles spent in Kernel mode",
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"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC:u / CPU_CLK_UNHALTED.REF_TSC",
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"MetricGroup": "Summary",
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"MetricName": "Kernel_Utilization"
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},
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{
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"BriefDescription": "C3 residency percent per core",
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"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C3_Core_Residency"
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},
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{
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"BriefDescription": "C6 residency percent per core",
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"MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C6_Core_Residency"
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},
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{
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"BriefDescription": "C7 residency percent per core",
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"MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C7_Core_Residency"
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},
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{
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"BriefDescription": "C2 residency percent per package",
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"MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C2_Pkg_Residency"
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},
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{
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"BriefDescription": "C3 residency percent per package",
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"MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C3_Pkg_Residency"
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},
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{
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"BriefDescription": "C6 residency percent per package",
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"MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C6_Pkg_Residency"
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},
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{
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"BriefDescription": "C7 residency percent per package",
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"MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
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"MetricGroup": "Power",
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"MetricName": "C7_Pkg_Residency"
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}
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]
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