mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 16:45:25 +07:00
14e25c5eeb
pmu_init no longer exists, so don't declare it in asm/pmu.h. Reported-by: Pawel Moll <Pawel.Moll@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
137 lines
3.4 KiB
C
137 lines
3.4 KiB
C
/*
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* linux/arch/arm/include/asm/pmu.h
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*
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* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ARM_PMU_H__
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#define __ARM_PMU_H__
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#include <linux/interrupt.h>
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#include <linux/perf_event.h>
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/*
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* Types of PMUs that can be accessed directly and require mutual
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* exclusion between profiling tools.
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*/
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enum arm_pmu_type {
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ARM_PMU_DEVICE_CPU = 0,
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ARM_NUM_PMU_DEVICES,
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};
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/*
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* struct arm_pmu_platdata - ARM PMU platform data
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*
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* @handle_irq: an optional handler which will be called from the interrupt and
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* passed the address of the low level handler, and can be used to implement
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* any platform specific handling before or after calling it.
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*/
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struct arm_pmu_platdata {
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irqreturn_t (*handle_irq)(int irq, void *dev,
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irq_handler_t pmu_handler);
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};
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#ifdef CONFIG_CPU_HAS_PMU
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/**
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* reserve_pmu() - reserve the hardware performance counters
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*
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* Reserve the hardware performance counters in the system for exclusive use.
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* Returns 0 on success or -EBUSY if the lock is already held.
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*/
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extern int
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reserve_pmu(enum arm_pmu_type type);
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/**
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* release_pmu() - Relinquish control of the performance counters
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*
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* Release the performance counters and allow someone else to use them.
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*/
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extern void
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release_pmu(enum arm_pmu_type type);
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#else /* CONFIG_CPU_HAS_PMU */
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#include <linux/err.h>
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static inline int
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reserve_pmu(enum arm_pmu_type type)
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{
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return -ENODEV;
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}
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static inline void
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release_pmu(enum arm_pmu_type type) { }
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#endif /* CONFIG_CPU_HAS_PMU */
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#ifdef CONFIG_HW_PERF_EVENTS
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/* The events for a given PMU register set. */
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struct pmu_hw_events {
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/*
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* The events that are active on the PMU for the given index.
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*/
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struct perf_event **events;
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/*
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* A 1 bit for an index indicates that the counter is being used for
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* an event. A 0 means that the counter can be used.
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*/
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unsigned long *used_mask;
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/*
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* Hardware lock to serialize accesses to PMU registers. Needed for the
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* read/modify/write sequences.
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*/
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raw_spinlock_t pmu_lock;
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};
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struct arm_pmu {
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struct pmu pmu;
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enum arm_perf_pmu_ids id;
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enum arm_pmu_type type;
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cpumask_t active_irqs;
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const char *name;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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void (*enable)(struct hw_perf_event *evt, int idx);
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void (*disable)(struct hw_perf_event *evt, int idx);
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int (*get_event_idx)(struct pmu_hw_events *hw_events,
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struct hw_perf_event *hwc);
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int (*set_event_filter)(struct hw_perf_event *evt,
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struct perf_event_attr *attr);
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u32 (*read_counter)(int idx);
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void (*write_counter)(int idx, u32 val);
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void (*start)(void);
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void (*stop)(void);
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void (*reset)(void *);
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int (*map_event)(struct perf_event *event);
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int num_events;
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atomic_t active_events;
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struct mutex reserve_mutex;
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u64 max_period;
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struct platform_device *plat_device;
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struct pmu_hw_events *(*get_hw_events)(void);
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};
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#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
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int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
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u64 armpmu_event_update(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx, int overflow);
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int armpmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx);
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#endif /* CONFIG_HW_PERF_EVENTS */
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#endif /* __ARM_PMU_H__ */
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