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14a1b8ca17
ADAU1373_BCLKDIV_SOURCE is defined as BIT(5) which uses UL constants. On amd64 the result of the ones complement operator is then truncated to unsigned int according to the prototype of snd_soc_update_bits(). I think gcc is correctly warning that the upper 32 bits are lost. sound/soc/codecs/adau1373.c: In function 'adau1373_hw_params': sound/soc/codecs/adau1373.c:940:3: warning: large integer implicitly truncated to unsigned type [-Woverflow] gcc version 4.6.3 Add 2 more BCLKDIV mask macros as explained by Lars: The BCLKDIV has three fields. The bitclock divider (bit 0-1), the samplerate (bit 2-4) and the source select (bit 5). Here we want to update the bitclock divider field and the samplerate field. When I wrote the code I was lazy and used ~ADAU1373_BCLKDIV_SOURCE as the mask, which for this register is functionally equivalent to ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK. Signed-off-by: Tim Gardner <tim.gardner@canonical.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> |
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| atmel | ||
| au1x | ||
| blackfin | ||
| cirrus | ||
| codecs | ||
| davinci | ||
| dwc | ||
| fsl | ||
| generic | ||
| jz4740 | ||
| kirkwood | ||
| mid-x86 | ||
| mxs | ||
| nuc900 | ||
| omap | ||
| pxa | ||
| s6000 | ||
| samsung | ||
| sh | ||
| spear | ||
| tegra | ||
| txx9 | ||
| ux500 | ||
| Kconfig | ||
| Makefile | ||
| soc-cache.c | ||
| soc-compress.c | ||
| soc-core.c | ||
| soc-dapm.c | ||
| soc-dmaengine-pcm.c | ||
| soc-io.c | ||
| soc-jack.c | ||
| soc-pcm.c | ||
| soc-utils.c | ||