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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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290 lines
6.1 KiB
C
290 lines
6.1 KiB
C
/*
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* arch/arm/mach-ixp23xx/pci.c
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*
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* PCI routines for IXP23XX based systems
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*
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* Copyright (c) 2005 MontaVista Software, Inc.
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*
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* based on original code:
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*
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* Author: Naeem Afzal <naeem.m.afzal@intel.com>
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* Copyright 2002-2005 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <asm/sizes.h>
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#include <asm/system.h>
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#include <asm/mach/pci.h>
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#include <mach/hardware.h>
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extern int (*external_fault) (unsigned long, struct pt_regs *);
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static volatile int pci_master_aborts = 0;
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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int clear_master_aborts(void);
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static u32
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*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
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{
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u32 *paddress;
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/*
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* Must be dword aligned
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*/
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where &= ~3;
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/*
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* For top bus, generate type 0, else type 1
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*/
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if (!bus_nr) {
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if (PCI_SLOT(devfn) >= 8)
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return 0;
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paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
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| (1 << (PCI_SLOT(devfn) + 16))
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| (PCI_FUNC(devfn) << 8) | where);
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} else {
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paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
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| (bus_nr << 16)
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| (PCI_SLOT(devfn) << 11)
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| (PCI_FUNC(devfn) << 8) | where);
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}
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return paddress;
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}
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/*
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* Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
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* 0 and 3 are not valid indexes...
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*/
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static u32 bytemask[] = {
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/*0*/ 0,
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/*1*/ 0xff,
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/*2*/ 0xffff,
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/*3*/ 0,
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/*4*/ 0xffffffff,
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};
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static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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u32 n;
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u32 *addr;
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n = where % 4;
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DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
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addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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pci_master_aborts = 0;
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*value = (*addr >> (8*n)) & bytemask[size];
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if (pci_master_aborts) {
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pci_master_aborts = 0;
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*value = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* We don't do error checking on the address for writes.
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* It's assumed that the user checked for the device existing first
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* by doing a read first.
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*/
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static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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u32 mask;
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u32 *addr;
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u32 temp;
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mask = ~(bytemask[size] << ((where % 0x4) * 8));
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addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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temp = (u32) (value) << ((where % 0x4) * 8);
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*addr = (*addr & mask) | temp;
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clear_master_aborts();
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops ixp23xx_pci_ops = {
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.read = ixp23xx_pci_read_config,
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.write = ixp23xx_pci_write_config,
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};
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struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
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{
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return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
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}
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int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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{
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volatile unsigned long temp;
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unsigned long flags;
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pci_master_aborts = 1;
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local_irq_save(flags);
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temp = *IXP23XX_PCI_CONTROL;
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/*
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* master abort and cmd tgt err
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*/
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if (temp & ((1 << 8) | (1 << 5)))
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*IXP23XX_PCI_CONTROL = temp;
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temp = *IXP23XX_PCI_CMDSTAT;
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if (temp & (1 << 29))
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*IXP23XX_PCI_CMDSTAT = temp;
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local_irq_restore(flags);
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/*
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* If it was an imprecise abort, then we need to correct the
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* return address to be _after_ the instruction.
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*/
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if (fsr & (1 << 10))
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regs->ARM_pc += 4;
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return 0;
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}
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int clear_master_aborts(void)
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{
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volatile u32 temp;
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temp = *IXP23XX_PCI_CONTROL;
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/*
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* master abort and cmd tgt err
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*/
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if (temp & ((1 << 8) | (1 << 5)))
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*IXP23XX_PCI_CONTROL = temp;
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temp = *IXP23XX_PCI_CMDSTAT;
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if (temp & (1 << 29))
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*IXP23XX_PCI_CMDSTAT = temp;
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return 0;
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}
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static void __init ixp23xx_pci_common_init(void)
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{
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#ifdef __ARMEB__
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*IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
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#endif
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/*
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* ADDR_31 needs to be clear for PCI memory access to CPP memory
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*/
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*IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
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*IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
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/*
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* Select correct memory for PCI inbound transactions
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*/
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if (ixp23xx_cpp_boot()) {
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*IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
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} else {
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*IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
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/*
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* Enable coherency on A2 silicon.
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*/
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if (arch_is_coherent())
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*IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
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}
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}
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void __init ixp23xx_pci_preinit(void)
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{
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ixp23xx_pci_common_init();
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hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
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"PCI config cycle to non-existent device");
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*IXP23XX_PCI_ADDR_EXT = 0x0000e000;
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}
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/*
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* Prevent PCI layer from seeing the inbound host-bridge resources
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*/
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static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
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{
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int i;
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dev->class &= 0xff;
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dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
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/*
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* IXP2300 systems often have large resource requirements, so we just
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* use our own resource space.
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*/
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static struct resource ixp23xx_pci_mem_space = {
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.start = IXP23XX_PCI_MEM_START,
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.end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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.name = "PCI Mem Space"
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};
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static struct resource ixp23xx_pci_io_space = {
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.start = 0x00000100,
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.end = 0x01ffffff,
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.flags = IORESOURCE_IO,
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.name = "PCI I/O Space"
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};
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int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
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{
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if (nr >= 1)
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return 0;
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sys->resource[0] = &ixp23xx_pci_io_space;
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sys->resource[1] = &ixp23xx_pci_mem_space;
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sys->resource[2] = NULL;
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return 1;
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}
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void __init ixp23xx_pci_slave_init(void)
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{
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ixp23xx_pci_common_init();
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}
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