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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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85fa0c7f8d
All Rockchip SoCs at least down to the ARM9-based RK28xx include the reset- controller for SoC peripherals in their clock controller. While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary. To be compatible with both schemes the reset controller takes a flag to decide which scheme to use, similar to the other HIWORD_MASK flags used in the clock framework. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
119 lines
3.1 KiB
C
119 lines
3.1 KiB
C
/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include "clk.h"
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struct rockchip_softrst {
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struct reset_controller_dev rcdev;
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void __iomem *reg_base;
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int num_regs;
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int num_per_reg;
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u8 flags;
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spinlock_t lock;
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};
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static int rockchip_softrst_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rockchip_softrst *softrst = container_of(rcdev,
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struct rockchip_softrst,
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rcdev);
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int bank = id / softrst->num_per_reg;
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int offset = id % softrst->num_per_reg;
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if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
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writel(BIT(offset) | (BIT(offset) << 16),
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softrst->reg_base + (bank * 4));
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} else {
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&softrst->lock, flags);
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reg = readl(softrst->reg_base + (bank * 4));
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writel(reg | BIT(offset), softrst->reg_base + (bank * 4));
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spin_unlock_irqrestore(&softrst->lock, flags);
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}
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return 0;
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}
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static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rockchip_softrst *softrst = container_of(rcdev,
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struct rockchip_softrst,
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rcdev);
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int bank = id / softrst->num_per_reg;
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int offset = id % softrst->num_per_reg;
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if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
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writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));
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} else {
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&softrst->lock, flags);
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reg = readl(softrst->reg_base + (bank * 4));
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writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4));
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spin_unlock_irqrestore(&softrst->lock, flags);
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}
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return 0;
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}
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static struct reset_control_ops rockchip_softrst_ops = {
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.assert = rockchip_softrst_assert,
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.deassert = rockchip_softrst_deassert,
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};
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void __init rockchip_register_softrst(struct device_node *np,
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unsigned int num_regs,
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void __iomem *base, u8 flags)
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{
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struct rockchip_softrst *softrst;
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int ret;
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softrst = kzalloc(sizeof(*softrst), GFP_KERNEL);
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if (!softrst)
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return;
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spin_lock_init(&softrst->lock);
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softrst->reg_base = base;
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softrst->flags = flags;
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softrst->num_regs = num_regs;
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softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16
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: 32;
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softrst->rcdev.owner = THIS_MODULE;
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softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg;
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softrst->rcdev.ops = &rockchip_softrst_ops;
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softrst->rcdev.of_node = np;
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ret = reset_controller_register(&softrst->rcdev);
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if (ret) {
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pr_err("%s: could not register reset controller, %d\n",
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__func__, ret);
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kfree(softrst);
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}
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};
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