Keerthy 147e541369 ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock ... Add divider table to optfclk_pciephy_div clock. The 8th bit of CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1 based on if the divider value is 0x2 or 0x1. Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the block diagram of Clock Generator Subsystem of PCIe PHY module. The divider value if '1' should be programmed in order to get the correct PCIE_PHY_DIV_GCLK frequency (2.5GHz). Cc: Rajendra Nayak <rnayak@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>		2014-07-15 00:16:09 -07:00
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compressed	Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into next	2014-06-05 15:57:04 -07:00
dts	ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock	2014-07-15 00:16:09 -07:00
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