mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 08:40:54 +07:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
/*
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* linux/include/asm-arm/arch-clps711x/uncompress.h
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/config.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/hardware/clps7111.h>
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#undef CLPS7111_BASE
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#define CLPS7111_BASE CLPS7111_PHYS_BASE
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#define barrier() __asm__ __volatile__("": : :"memory")
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#define __raw_readl(p) (*(unsigned long *)(p))
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#define __raw_writel(v,p) (*(unsigned long *)(p) = (v))
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#ifdef CONFIG_DEBUG_CLPS711X_UART2
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#define SYSFLGx SYSFLG2
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#define UARTDRx UARTDR2
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#else
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#define SYSFLGx SYSFLG1
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#define UARTDRx UARTDR1
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#endif
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/*
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* This does not append a newline
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*/
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static void putstr(const char *s)
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{
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char c;
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while ((c = *s++) != '\0') {
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while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
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barrier();
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clps_writel(c, UARTDRx);
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if (c == '\n') {
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while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
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barrier();
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clps_writel('\r', UARTDRx);
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}
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}
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while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
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barrier();
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}
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/*
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* nothing to do
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*/
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#define arch_decomp_setup()
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#define arch_decomp_wdog()
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