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457f218095
The current uaccess code uses a page table walk in some circumstances,
e.g. in case of the in atomic futex operations or if running on old
hardware which doesn't support the mvcos instruction.
However it turned out that the page table walk code does not correctly
lock page tables when accessing page table entries.
In other words: a different cpu may invalidate a page table entry while
the current cpu inspects the pte. This may lead to random data corruption.
Adding correct locking however isn't trivial for all uaccess operations.
Especially copy_in_user() is problematic since that requires to hold at
least two locks, but must be protected against ABBA deadlock when a
different cpu also performs a copy_in_user() operation.
So the solution is a different approach where we change address spaces:
User space runs in primary address mode, or access register mode within
vdso code, like it currently already does.
The kernel usually also runs in home space mode, however when accessing
user space the kernel switches to primary or secondary address mode if
the mvcos instruction is not available or if a compare-and-swap (futex)
instruction on a user space address is performed.
KVM however is special, since that requires the kernel to run in home
address space while implicitly accessing user space with the sie
instruction.
So we end up with:
User space:
- runs in primary or access register mode
- cr1 contains the user asce
- cr7 contains the user asce
- cr13 contains the kernel asce
Kernel space:
- runs in home space mode
- cr1 contains the user or kernel asce
-> the kernel asce is loaded when a uaccess requires primary or
secondary address mode
- cr7 contains the user or kernel asce, (changed with set_fs())
- cr13 contains the kernel asce
In case of uaccess the kernel changes to:
- primary space mode in case of a uaccess (copy_to_user) and uses
e.g. the mvcp instruction to access user space. However the kernel
will stay in home space mode if the mvcos instruction is available
- secondary space mode in case of futex atomic operations, so that the
instructions come from primary address space and data from secondary
space
In case of kvm the kernel runs in home space mode, but cr1 gets switched
to contain the gmap asce before the sie instruction gets executed. When
the sie instruction is finished cr1 will be switched back to contain the
user asce.
A context switch between two processes will always load the kernel asce
for the next process in cr1. So the first exit to user space is a bit
more expensive (one extra load control register instruction) than before,
however keeps the code rather simple.
In sum this means there is no need to perform any error prone page table
walks anymore when accessing user space.
The patch seems to be rather large, however it mainly removes the
the page table walk code and restores the previously deleted "standard"
uaccess code, with a couple of changes.
The uaccess without mvcos mode can be enforced with the "uaccess_primary"
kernel parameter.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
/*
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* Copyright IBM Corp. 1999, 2009
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#ifndef __ASM_SWITCH_TO_H
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#define __ASM_SWITCH_TO_H
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#include <linux/thread_info.h>
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#include <asm/ptrace.h>
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extern struct task_struct *__switch_to(void *, void *);
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extern void update_cr_regs(struct task_struct *task);
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static inline int test_fp_ctl(u32 fpc)
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{
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u32 orig_fpc;
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int rc;
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if (!MACHINE_HAS_IEEE)
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return 0;
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asm volatile(
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" efpc %1\n"
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" sfpc %2\n"
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"0: sfpc %1\n"
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" la %0,0\n"
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"1:\n"
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EX_TABLE(0b,1b)
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: "=d" (rc), "=d" (orig_fpc)
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: "d" (fpc), "0" (-EINVAL));
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return rc;
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}
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static inline void save_fp_ctl(u32 *fpc)
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{
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile(
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" stfpc %0\n"
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: "+Q" (*fpc));
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}
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static inline int restore_fp_ctl(u32 *fpc)
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{
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int rc;
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if (!MACHINE_HAS_IEEE)
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return 0;
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asm volatile(
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"0: lfpc %1\n"
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" la %0,0\n"
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"1:\n"
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EX_TABLE(0b,1b)
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: "=d" (rc) : "Q" (*fpc), "0" (-EINVAL));
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return rc;
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}
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static inline void save_fp_regs(freg_t *fprs)
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{
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asm volatile("std 0,%0" : "=Q" (fprs[0]));
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asm volatile("std 2,%0" : "=Q" (fprs[2]));
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asm volatile("std 4,%0" : "=Q" (fprs[4]));
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asm volatile("std 6,%0" : "=Q" (fprs[6]));
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile("std 1,%0" : "=Q" (fprs[1]));
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asm volatile("std 3,%0" : "=Q" (fprs[3]));
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asm volatile("std 5,%0" : "=Q" (fprs[5]));
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asm volatile("std 7,%0" : "=Q" (fprs[7]));
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asm volatile("std 8,%0" : "=Q" (fprs[8]));
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asm volatile("std 9,%0" : "=Q" (fprs[9]));
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asm volatile("std 10,%0" : "=Q" (fprs[10]));
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asm volatile("std 11,%0" : "=Q" (fprs[11]));
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asm volatile("std 12,%0" : "=Q" (fprs[12]));
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asm volatile("std 13,%0" : "=Q" (fprs[13]));
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asm volatile("std 14,%0" : "=Q" (fprs[14]));
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asm volatile("std 15,%0" : "=Q" (fprs[15]));
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}
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static inline void restore_fp_regs(freg_t *fprs)
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{
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asm volatile("ld 0,%0" : : "Q" (fprs[0]));
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asm volatile("ld 2,%0" : : "Q" (fprs[2]));
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asm volatile("ld 4,%0" : : "Q" (fprs[4]));
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asm volatile("ld 6,%0" : : "Q" (fprs[6]));
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile("ld 1,%0" : : "Q" (fprs[1]));
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asm volatile("ld 3,%0" : : "Q" (fprs[3]));
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asm volatile("ld 5,%0" : : "Q" (fprs[5]));
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asm volatile("ld 7,%0" : : "Q" (fprs[7]));
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asm volatile("ld 8,%0" : : "Q" (fprs[8]));
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asm volatile("ld 9,%0" : : "Q" (fprs[9]));
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asm volatile("ld 10,%0" : : "Q" (fprs[10]));
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asm volatile("ld 11,%0" : : "Q" (fprs[11]));
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asm volatile("ld 12,%0" : : "Q" (fprs[12]));
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asm volatile("ld 13,%0" : : "Q" (fprs[13]));
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asm volatile("ld 14,%0" : : "Q" (fprs[14]));
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asm volatile("ld 15,%0" : : "Q" (fprs[15]));
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}
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static inline void save_access_regs(unsigned int *acrs)
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{
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typedef struct { int _[NUM_ACRS]; } acrstype;
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asm volatile("stam 0,15,%0" : "=Q" (*(acrstype *)acrs));
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}
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static inline void restore_access_regs(unsigned int *acrs)
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{
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typedef struct { int _[NUM_ACRS]; } acrstype;
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asm volatile("lam 0,15,%0" : : "Q" (*(acrstype *)acrs));
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}
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#define switch_to(prev,next,last) do { \
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if (prev->mm) { \
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save_fp_ctl(&prev->thread.fp_regs.fpc); \
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save_fp_regs(prev->thread.fp_regs.fprs); \
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save_access_regs(&prev->thread.acrs[0]); \
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save_ri_cb(prev->thread.ri_cb); \
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} \
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if (next->mm) { \
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restore_fp_ctl(&next->thread.fp_regs.fpc); \
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restore_fp_regs(next->thread.fp_regs.fprs); \
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restore_access_regs(&next->thread.acrs[0]); \
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restore_ri_cb(next->thread.ri_cb, prev->thread.ri_cb); \
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update_cr_regs(next); \
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} \
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prev = __switch_to(prev,next); \
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update_primary_asce(current); \
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} while (0)
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#define finish_arch_switch(prev) do { \
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set_fs(current->thread.mm_segment); \
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} while (0)
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#endif /* __ASM_SWITCH_TO_H */
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