mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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07613ba2f4
This switches AGP to use an array of pages for tracking the pages allocated to the GART. This should enable GEM on PAE to work a lot better as we can pass highmem pages to the PAT code and it will do the right thing with them. Signed-off-by: Dave Airlie <airlied@redhat.com>
370 lines
11 KiB
C
370 lines
11 KiB
C
/*
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* AGPGART
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* Copyright (C) 2004 Silicon Graphics, Inc.
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* Copyright (C) 2002-2004 Dave Jones
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* Copyright (C) 1999 Jeff Hartmann
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* Copyright (C) 1999 Precision Insight, Inc.
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* Copyright (C) 1999 Xi Graphics, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
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* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _AGP_BACKEND_PRIV_H
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#define _AGP_BACKEND_PRIV_H 1
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#include <asm/agp.h> /* for flush_agp_cache() */
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#define PFX "agpgart: "
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//#define AGP_DEBUG 1
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#ifdef AGP_DEBUG
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#define DBG(x,y...) printk (KERN_DEBUG PFX "%s: " x "\n", __func__ , ## y)
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#else
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#define DBG(x,y...) do { } while (0)
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#endif
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extern struct agp_bridge_data *agp_bridge;
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enum aper_size_type {
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U8_APER_SIZE,
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U16_APER_SIZE,
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U32_APER_SIZE,
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LVL2_APER_SIZE,
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FIXED_APER_SIZE
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};
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struct gatt_mask {
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unsigned long mask;
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u32 type;
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/* totally device specific, for integrated chipsets that
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* might have different types of memory masks. For other
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* devices this will probably be ignored */
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};
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#define AGP_PAGE_DESTROY_UNMAP 1
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#define AGP_PAGE_DESTROY_FREE 2
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struct aper_size_info_8 {
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int size;
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int num_entries;
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int page_order;
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u8 size_value;
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};
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struct aper_size_info_16 {
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int size;
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int num_entries;
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int page_order;
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u16 size_value;
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};
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struct aper_size_info_32 {
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int size;
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int num_entries;
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int page_order;
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u32 size_value;
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};
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struct aper_size_info_lvl2 {
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int size;
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int num_entries;
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u32 size_value;
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};
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struct aper_size_info_fixed {
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int size;
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int num_entries;
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int page_order;
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};
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struct agp_bridge_driver {
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struct module *owner;
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const void *aperture_sizes;
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int num_aperture_sizes;
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enum aper_size_type size_type;
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bool cant_use_aperture;
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bool needs_scratch_page;
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const struct gatt_mask *masks;
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int (*fetch_size)(void);
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int (*configure)(void);
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void (*agp_enable)(struct agp_bridge_data *, u32);
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void (*cleanup)(void);
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void (*tlb_flush)(struct agp_memory *);
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unsigned long (*mask_memory)(struct agp_bridge_data *, struct page *, int);
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void (*cache_flush)(void);
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int (*create_gatt_table)(struct agp_bridge_data *);
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int (*free_gatt_table)(struct agp_bridge_data *);
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int (*insert_memory)(struct agp_memory *, off_t, int);
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int (*remove_memory)(struct agp_memory *, off_t, int);
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struct agp_memory *(*alloc_by_type) (size_t, int);
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void (*free_by_type)(struct agp_memory *);
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struct page *(*agp_alloc_page)(struct agp_bridge_data *);
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int (*agp_alloc_pages)(struct agp_bridge_data *, struct agp_memory *, size_t);
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void (*agp_destroy_page)(struct page *, int flags);
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void (*agp_destroy_pages)(struct agp_memory *);
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int (*agp_type_to_mask_type) (struct agp_bridge_data *, int);
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void (*chipset_flush)(struct agp_bridge_data *);
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};
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struct agp_bridge_data {
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const struct agp_version *version;
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const struct agp_bridge_driver *driver;
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struct vm_operations_struct *vm_ops;
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void *previous_size;
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void *current_size;
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void *dev_private_data;
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struct pci_dev *dev;
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u32 __iomem *gatt_table;
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u32 *gatt_table_real;
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unsigned long scratch_page;
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unsigned long scratch_page_real;
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unsigned long gart_bus_addr;
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unsigned long gatt_bus_addr;
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u32 mode;
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enum chipset_type type;
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unsigned long *key_list;
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atomic_t current_memory_agp;
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atomic_t agp_in_use;
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int max_memory_agp; /* in number of pages */
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int aperture_size_idx;
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int capndx;
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int flags;
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char major_version;
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char minor_version;
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struct list_head list;
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u32 apbase_config;
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/* list of agp_memory mapped to the aperture */
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struct list_head mapped_list;
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spinlock_t mapped_lock;
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};
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#define KB(x) ((x) * 1024)
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#define MB(x) (KB (KB (x)))
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#define GB(x) (MB (KB (x)))
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#define A_SIZE_8(x) ((struct aper_size_info_8 *) x)
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#define A_SIZE_16(x) ((struct aper_size_info_16 *) x)
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#define A_SIZE_32(x) ((struct aper_size_info_32 *) x)
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#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x)
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#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x)
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#define A_IDX8(bridge) (A_SIZE_8((bridge)->driver->aperture_sizes) + i)
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#define A_IDX16(bridge) (A_SIZE_16((bridge)->driver->aperture_sizes) + i)
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#define A_IDX32(bridge) (A_SIZE_32((bridge)->driver->aperture_sizes) + i)
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#define MAXKEY (4096 * 32)
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#define PGE_EMPTY(b, p) (!(p) || (p) == (unsigned long) (b)->scratch_page)
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/* Intel registers */
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#define INTEL_APSIZE 0xb4
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#define INTEL_ATTBASE 0xb8
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#define INTEL_AGPCTRL 0xb0
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#define INTEL_NBXCFG 0x50
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#define INTEL_ERRSTS 0x91
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/* Intel i830 registers */
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#define I830_GMCH_CTRL 0x52
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#define I830_GMCH_ENABLED 0x4
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#define I830_GMCH_MEM_MASK 0x1
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#define I830_GMCH_MEM_64M 0x1
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#define I830_GMCH_MEM_128M 0
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#define I830_GMCH_GMS_MASK 0x70
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#define I830_GMCH_GMS_DISABLED 0x00
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#define I830_GMCH_GMS_LOCAL 0x10
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#define I830_GMCH_GMS_STOLEN_512 0x20
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#define I830_GMCH_GMS_STOLEN_1024 0x30
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#define I830_GMCH_GMS_STOLEN_8192 0x40
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#define I830_RDRAM_CHANNEL_TYPE 0x03010
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#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
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#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
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/* This one is for I830MP w. an external graphic card */
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#define INTEL_I830_ERRSTS 0x92
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/* Intel 855GM/852GM registers */
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#define I855_GMCH_GMS_MASK 0xF0
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#define I855_GMCH_GMS_STOLEN_0M 0x0
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#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
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#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
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#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
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#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
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#define I85X_CAPID 0x44
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#define I85X_VARIANT_MASK 0x7
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#define I85X_VARIANT_SHIFT 5
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#define I855_GME 0x0
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#define I855_GM 0x4
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#define I852_GME 0x2
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#define I852_GM 0x5
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/* Intel i845 registers */
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#define INTEL_I845_AGPM 0x51
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#define INTEL_I845_ERRSTS 0xc8
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/* Intel i860 registers */
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#define INTEL_I860_MCHCFG 0x50
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#define INTEL_I860_ERRSTS 0xc8
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/* Intel i810 registers */
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#define I810_GMADDR 0x10
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#define I810_MMADDR 0x14
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#define I810_PTE_BASE 0x10000
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#define I810_PTE_MAIN_UNCACHED 0x00000000
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#define I810_PTE_LOCAL 0x00000002
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#define I810_PTE_VALID 0x00000001
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#define I830_PTE_SYSTEM_CACHED 0x00000006
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#define I810_SMRAM_MISCC 0x70
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#define I810_GFX_MEM_WIN_SIZE 0x00010000
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#define I810_GFX_MEM_WIN_32M 0x00010000
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#define I810_GMS 0x000000c0
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#define I810_GMS_DISABLE 0x00000000
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#define I810_PGETBL_CTL 0x2020
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#define I810_PGETBL_ENABLED 0x00000001
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#define I965_PGETBL_SIZE_MASK 0x0000000e
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#define I965_PGETBL_SIZE_512KB (0 << 1)
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#define I965_PGETBL_SIZE_256KB (1 << 1)
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#define I965_PGETBL_SIZE_128KB (2 << 1)
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#define I965_PGETBL_SIZE_1MB (3 << 1)
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#define I965_PGETBL_SIZE_2MB (4 << 1)
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#define I965_PGETBL_SIZE_1_5MB (5 << 1)
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#define G33_PGETBL_SIZE_MASK (3 << 8)
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#define G33_PGETBL_SIZE_1M (1 << 8)
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#define G33_PGETBL_SIZE_2M (2 << 8)
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#define I810_DRAM_CTL 0x3000
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#define I810_DRAM_ROW_0 0x00000001
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#define I810_DRAM_ROW_0_SDRAM 0x00000001
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struct agp_device_ids {
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unsigned short device_id; /* first, to make table easier to read */
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enum chipset_type chipset;
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const char *chipset_name;
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int (*chipset_setup) (struct pci_dev *pdev); /* used to override generic */
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};
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/* Driver registration */
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struct agp_bridge_data *agp_alloc_bridge(void);
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void agp_put_bridge(struct agp_bridge_data *bridge);
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int agp_add_bridge(struct agp_bridge_data *bridge);
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void agp_remove_bridge(struct agp_bridge_data *bridge);
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/* Frontend routines. */
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int agp_frontend_initialize(void);
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void agp_frontend_cleanup(void);
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/* Generic routines. */
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void agp_generic_enable(struct agp_bridge_data *bridge, u32 mode);
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int agp_generic_create_gatt_table(struct agp_bridge_data *bridge);
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int agp_generic_free_gatt_table(struct agp_bridge_data *bridge);
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struct agp_memory *agp_create_memory(int scratch_pages);
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int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type);
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int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type);
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struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type);
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void agp_generic_free_by_type(struct agp_memory *curr);
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struct page *agp_generic_alloc_page(struct agp_bridge_data *bridge);
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int agp_generic_alloc_pages(struct agp_bridge_data *agp_bridge,
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struct agp_memory *memory, size_t page_count);
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void agp_generic_destroy_page(struct page *page, int flags);
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void agp_generic_destroy_pages(struct agp_memory *memory);
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void agp_free_key(int key);
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int agp_num_entries(void);
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u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command);
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void agp_device_command(u32 command, bool agp_v3);
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int agp_3_5_enable(struct agp_bridge_data *bridge);
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void global_cache_flush(void);
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void get_agp_version(struct agp_bridge_data *bridge);
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unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
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struct page *page, int type);
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int agp_generic_type_to_mask_type(struct agp_bridge_data *bridge,
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int type);
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struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev);
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/* generic functions for user-populated AGP memory types */
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struct agp_memory *agp_generic_alloc_user(size_t page_count, int type);
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void agp_alloc_page_array(size_t size, struct agp_memory *mem);
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void agp_free_page_array(struct agp_memory *mem);
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/* generic routines for agp>=3 */
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int agp3_generic_fetch_size(void);
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void agp3_generic_tlbflush(struct agp_memory *mem);
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int agp3_generic_configure(void);
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void agp3_generic_cleanup(void);
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/* aperture sizes have been standardised since v3 */
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#define AGP_GENERIC_SIZES_ENTRIES 11
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extern const struct aper_size_info_16 agp3_generic_sizes[];
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#define virt_to_gart(x) (phys_to_gart(virt_to_phys(x)))
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#define gart_to_virt(x) (phys_to_virt(gart_to_phys(x)))
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extern int agp_off;
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extern int agp_try_unsupported_boot;
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long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
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/* Chipset independant registers (from AGP Spec) */
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#define AGP_APBASE 0x10
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#define AGPSTAT 0x4
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#define AGPCMD 0x8
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#define AGPNISTAT 0xc
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#define AGPCTRL 0x10
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#define AGPAPSIZE 0x14
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#define AGPNEPG 0x16
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#define AGPGARTLO 0x18
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#define AGPGARTHI 0x1c
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#define AGPNICMD 0x20
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#define AGP_MAJOR_VERSION_SHIFT (20)
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#define AGP_MINOR_VERSION_SHIFT (16)
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#define AGPSTAT_RQ_DEPTH (0xff000000)
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#define AGPSTAT_RQ_DEPTH_SHIFT 24
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#define AGPSTAT_CAL_MASK (1<<12|1<<11|1<<10)
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#define AGPSTAT_ARQSZ (1<<15|1<<14|1<<13)
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#define AGPSTAT_ARQSZ_SHIFT 13
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#define AGPSTAT_SBA (1<<9)
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#define AGPSTAT_AGP_ENABLE (1<<8)
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#define AGPSTAT_FW (1<<4)
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#define AGPSTAT_MODE_3_0 (1<<3)
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#define AGPSTAT2_1X (1<<0)
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#define AGPSTAT2_2X (1<<1)
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#define AGPSTAT2_4X (1<<2)
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#define AGPSTAT3_RSVD (1<<2)
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#define AGPSTAT3_8X (1<<1)
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#define AGPSTAT3_4X (1)
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#define AGPCTRL_APERENB (1<<8)
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#define AGPCTRL_GTLBEN (1<<7)
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#define AGP2_RESERVED_MASK 0x00fffcc8
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#define AGP3_RESERVED_MASK 0x00ff00c4
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#define AGP_ERRATA_FASTWRITES 1<<0
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#define AGP_ERRATA_SBA 1<<1
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#define AGP_ERRATA_1X 1<<2
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#endif /* _AGP_BACKEND_PRIV_H */
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