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c4b34a3b7a
This adds omap control module support for USBSS in AM437x SoC. Update DT binding information to reflect these changes. Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: George Cherian <george.cherian@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
103 lines
3.5 KiB
Plaintext
103 lines
3.5 KiB
Plaintext
OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
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OMAP MUSB GLUE
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- compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
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- ti,hwmods : must be "usb_otg_hs"
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- multipoint : Should be "1" indicating the musb controller supports
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multipoint. This is a MUSB configuration-specific setting.
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- num-eps : Specifies the number of endpoints. This is also a
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MUSB configuration-specific setting. Should be set to "16"
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- ram-bits : Specifies the ram address size. Should be set to "12"
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- interface-type : This is a board specific setting to describe the type of
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interface between the controller and the phy. It should be "0" or "1"
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specifying ULPI and UTMI respectively.
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- mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
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represents PERIPHERAL.
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- power : Should be "50". This signifies the controller can supply up to
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100mA when operating in host mode.
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- usb-phy : the phandle for the PHY device
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- phys : the phandle for the PHY device (used by generic PHY framework)
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- phy-names : the names of the PHY corresponding to the PHYs present in the
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*phy* phandle.
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Optional properties:
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- ctrl-module : phandle of the control module this glue uses to write to
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mailbox
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SOC specific device node entry
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usb_otg_hs: usb_otg_hs@4a0ab000 {
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compatible = "ti,omap4-musb";
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ti,hwmods = "usb_otg_hs";
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multipoint = <1>;
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num-eps = <16>;
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ram-bits = <12>;
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ctrl-module = <&omap_control_usb>;
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phys = <&usb2_phy>;
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phy-names = "usb2-phy";
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};
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Board specific device node entry
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&usb_otg_hs {
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interface-type = <1>;
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mode = <3>;
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power = <50>;
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};
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OMAP DWC3 GLUE
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- compatible : Should be "ti,dwc3"
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- ti,hwmods : Should be "usb_otg_ss"
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- reg : Address and length of the register set for the device.
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- interrupts : The irq number of this device that is used to interrupt the
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MPU
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- #address-cells, #size-cells : Must be present if the device has sub-nodes
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- utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
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It should be set to "1" for HW mode and "2" for SW mode.
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- ranges: the child address space are mapped 1:1 onto the parent address space
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Optional Properties:
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- extcon : phandle for the extcon device omap dwc3 uses to detect
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connect/disconnect events.
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- vbus-supply : phandle to the regulator device tree node if needed.
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Sub-nodes:
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The dwc3 core should be added as subnode to omap dwc3 glue.
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- dwc3 :
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The binding details of dwc3 can be found in:
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Documentation/devicetree/bindings/usb/dwc3.txt
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omap_dwc3 {
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compatible = "ti,dwc3";
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ti,hwmods = "usb_otg_ss";
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reg = <0x4a020000 0x1ff>;
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interrupts = <0 93 4>;
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#address-cells = <1>;
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#size-cells = <1>;
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utmi-mode = <2>;
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ranges;
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};
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OMAP CONTROL USB
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Required properties:
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- compatible: Should be one of
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"ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
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"ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
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e.g. USB2_PHY on OMAP5.
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"ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
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e.g. USB3 PHY and SATA PHY on OMAP5.
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"ti,control-phy-dra7usb2" - if it has power down register like USB2 PHY on
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DRA7 platform.
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"ti,control-phy-am437usb2" - if it has power down register like USB2 PHY on
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AM437 platform.
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- reg : Address and length of the register set for the device. It contains
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the address of "otghs_control" for control-phy-otghs or "power" register
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for other types.
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- reg-names: should be "otghs_control" control-phy-otghs and "power" for
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other types.
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omap_control_usb: omap-control-usb@4a002300 {
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compatible = "ti,control-phy-otghs";
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reg = <0x4a00233c 0x4>;
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reg-names = "otghs_control";
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};
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