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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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20c3a2c33e
Different AMD processors may have different implementations of STIBP. When STIBP is conditionally enabled, some implementations would benefit from having STIBP always on instead of toggling the STIBP bit through MSR writes. This preference is advertised through a CPUID feature bit. When conditional STIBP support is requested at boot and the CPU advertises STIBP always-on mode as preferred, switch to STIBP "on" support. To show that this transition has occurred, create a new spectre_v2_user_mitigation value and a new spectre_v2_user_strings message. The new mitigation value is used in spectre_v2_user_select_mitigation() to print the new mitigation message as well as to return a new string from stibp_state(). Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Borislav Petkov <bp@alien8.de> Cc: Tim Chen <tim.c.chen@linux.intel.com> Cc: David Woodhouse <dwmw@amazon.co.uk> Link: https://lkml.kernel.org/r/20181213230352.6937.74943.stgit@tlendack-t1.amdoffice.net
383 lines
10 KiB
C
383 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_NOSPEC_BRANCH_H_
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#define _ASM_X86_NOSPEC_BRANCH_H_
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#include <linux/static_key.h>
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#include <asm/alternative.h>
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#include <asm/alternative-asm.h>
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#include <asm/cpufeatures.h>
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#include <asm/msr-index.h>
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/*
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* Fill the CPU return stack buffer.
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*
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* Each entry in the RSB, if used for a speculative 'ret', contains an
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* infinite 'pause; lfence; jmp' loop to capture speculative execution.
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*
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* This is required in various cases for retpoline and IBRS-based
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* mitigations for the Spectre variant 2 vulnerability. Sometimes to
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* eliminate potentially bogus entries from the RSB, and sometimes
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* purely to ensure that it doesn't get empty, which on some CPUs would
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* allow predictions from other (unwanted!) sources to be used.
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*
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* We define a CPP macro such that it can be used from both .S files and
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* inline assembly. It's possible to do a .macro and then include that
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* from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
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*/
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#define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
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#define RSB_FILL_LOOPS 16 /* To avoid underflow */
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/*
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* Google experimented with loop-unrolling and this turned out to be
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* the optimal version — two calls, each with their own speculation
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* trap should their return address end up getting used, in a loop.
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*/
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#define __FILL_RETURN_BUFFER(reg, nr, sp) \
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mov $(nr/2), reg; \
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771: \
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call 772f; \
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773: /* speculation trap */ \
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pause; \
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lfence; \
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jmp 773b; \
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772: \
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call 774f; \
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775: /* speculation trap */ \
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pause; \
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lfence; \
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jmp 775b; \
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774: \
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dec reg; \
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jnz 771b; \
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add $(BITS_PER_LONG/8) * nr, sp;
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#ifdef __ASSEMBLY__
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/*
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* This should be used immediately before a retpoline alternative. It tells
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* objtool where the retpolines are so that it can make sense of the control
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* flow by just reading the original instruction(s) and ignoring the
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* alternatives.
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*/
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.macro ANNOTATE_NOSPEC_ALTERNATIVE
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.Lannotate_\@:
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.pushsection .discard.nospec
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.long .Lannotate_\@ - .
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.popsection
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.endm
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/*
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* This should be used immediately before an indirect jump/call. It tells
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* objtool the subsequent indirect jump/call is vouched safe for retpoline
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* builds.
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*/
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.macro ANNOTATE_RETPOLINE_SAFE
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.Lannotate_\@:
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.pushsection .discard.retpoline_safe
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_ASM_PTR .Lannotate_\@
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.popsection
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.endm
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/*
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* These are the bare retpoline primitives for indirect jmp and call.
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* Do not use these directly; they only exist to make the ALTERNATIVE
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* invocation below less ugly.
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*/
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.macro RETPOLINE_JMP reg:req
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call .Ldo_rop_\@
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.Lspec_trap_\@:
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pause
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lfence
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jmp .Lspec_trap_\@
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.Ldo_rop_\@:
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mov \reg, (%_ASM_SP)
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ret
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.endm
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/*
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* This is a wrapper around RETPOLINE_JMP so the called function in reg
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* returns to the instruction after the macro.
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*/
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.macro RETPOLINE_CALL reg:req
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jmp .Ldo_call_\@
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.Ldo_retpoline_jmp_\@:
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RETPOLINE_JMP \reg
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.Ldo_call_\@:
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call .Ldo_retpoline_jmp_\@
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.endm
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/*
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* JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
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* indirect jmp/call which may be susceptible to the Spectre variant 2
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* attack.
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*/
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.macro JMP_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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ANNOTATE_NOSPEC_ALTERNATIVE
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ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *\reg), \
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__stringify(RETPOLINE_JMP \reg), X86_FEATURE_RETPOLINE, \
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__stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *\reg), X86_FEATURE_RETPOLINE_AMD
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#else
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jmp *\reg
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#endif
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.endm
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.macro CALL_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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ANNOTATE_NOSPEC_ALTERNATIVE
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ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *\reg), \
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__stringify(RETPOLINE_CALL \reg), X86_FEATURE_RETPOLINE,\
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__stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *\reg), X86_FEATURE_RETPOLINE_AMD
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#else
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call *\reg
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#endif
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.endm
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/*
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* A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
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* monstrosity above, manually.
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*/
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.macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
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#ifdef CONFIG_RETPOLINE
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ANNOTATE_NOSPEC_ALTERNATIVE
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ALTERNATIVE "jmp .Lskip_rsb_\@", \
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__stringify(__FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP)) \
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\ftr
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.Lskip_rsb_\@:
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#endif
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.endm
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#else /* __ASSEMBLY__ */
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#define ANNOTATE_NOSPEC_ALTERNATIVE \
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"999:\n\t" \
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".pushsection .discard.nospec\n\t" \
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".long 999b - .\n\t" \
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".popsection\n\t"
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#define ANNOTATE_RETPOLINE_SAFE \
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"999:\n\t" \
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".pushsection .discard.retpoline_safe\n\t" \
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_ASM_PTR " 999b\n\t" \
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".popsection\n\t"
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#ifdef CONFIG_RETPOLINE
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#ifdef CONFIG_X86_64
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/*
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* Inline asm uses the %V modifier which is only in newer GCC
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* which is ensured when CONFIG_RETPOLINE is defined.
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*/
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# define CALL_NOSPEC \
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ANNOTATE_NOSPEC_ALTERNATIVE \
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ALTERNATIVE_2( \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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"call __x86_indirect_thunk_%V[thunk_target]\n", \
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X86_FEATURE_RETPOLINE, \
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"lfence;\n" \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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X86_FEATURE_RETPOLINE_AMD)
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# define THUNK_TARGET(addr) [thunk_target] "r" (addr)
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#else /* CONFIG_X86_32 */
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/*
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* For i386 we use the original ret-equivalent retpoline, because
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* otherwise we'll run out of registers. We don't care about CET
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* here, anyway.
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*/
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# define CALL_NOSPEC \
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ANNOTATE_NOSPEC_ALTERNATIVE \
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ALTERNATIVE_2( \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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" jmp 904f;\n" \
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" .align 16\n" \
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"901: call 903f;\n" \
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"902: pause;\n" \
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" lfence;\n" \
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" jmp 902b;\n" \
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" .align 16\n" \
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"903: addl $4, %%esp;\n" \
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" pushl %[thunk_target];\n" \
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" ret;\n" \
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" .align 16\n" \
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"904: call 901b;\n", \
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X86_FEATURE_RETPOLINE, \
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"lfence;\n" \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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X86_FEATURE_RETPOLINE_AMD)
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# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
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#endif
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#else /* No retpoline for C / inline asm */
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# define CALL_NOSPEC "call *%[thunk_target]\n"
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# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
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#endif
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/* The Spectre V2 mitigation variants */
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enum spectre_v2_mitigation {
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SPECTRE_V2_NONE,
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SPECTRE_V2_RETPOLINE_GENERIC,
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SPECTRE_V2_RETPOLINE_AMD,
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SPECTRE_V2_IBRS_ENHANCED,
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};
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/* The indirect branch speculation control variants */
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enum spectre_v2_user_mitigation {
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SPECTRE_V2_USER_NONE,
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SPECTRE_V2_USER_STRICT,
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SPECTRE_V2_USER_STRICT_PREFERRED,
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SPECTRE_V2_USER_PRCTL,
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SPECTRE_V2_USER_SECCOMP,
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};
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/* The Speculative Store Bypass disable variants */
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enum ssb_mitigation {
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SPEC_STORE_BYPASS_NONE,
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SPEC_STORE_BYPASS_DISABLE,
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SPEC_STORE_BYPASS_PRCTL,
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SPEC_STORE_BYPASS_SECCOMP,
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};
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extern char __indirect_thunk_start[];
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extern char __indirect_thunk_end[];
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/*
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* On VMEXIT we must ensure that no RSB predictions learned in the guest
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* can be followed in the host, by overwriting the RSB completely. Both
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* retpoline and IBRS mitigations for Spectre v2 need this; only on future
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* CPUs with IBRS_ALL *might* it be avoided.
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*/
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static inline void vmexit_fill_RSB(void)
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{
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#ifdef CONFIG_RETPOLINE
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unsigned long loops;
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asm volatile (ANNOTATE_NOSPEC_ALTERNATIVE
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ALTERNATIVE("jmp 910f",
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__stringify(__FILL_RETURN_BUFFER(%0, RSB_CLEAR_LOOPS, %1)),
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X86_FEATURE_RETPOLINE)
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"910:"
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: "=r" (loops), ASM_CALL_CONSTRAINT
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: : "memory" );
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#endif
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}
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static __always_inline
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void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
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{
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asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
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: : "c" (msr),
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"a" ((u32)val),
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"d" ((u32)(val >> 32)),
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[feature] "i" (feature)
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: "memory");
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}
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static inline void indirect_branch_prediction_barrier(void)
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{
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u64 val = PRED_CMD_IBPB;
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alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
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}
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/* The Intel SPEC CTRL MSR base value cache */
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extern u64 x86_spec_ctrl_base;
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/*
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* With retpoline, we must use IBRS to restrict branch prediction
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* before calling into firmware.
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*
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* (Implemented as CPP macros due to header hell.)
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*/
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#define firmware_restrict_branch_speculation_start() \
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do { \
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u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS; \
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\
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preempt_disable(); \
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alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
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X86_FEATURE_USE_IBRS_FW); \
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} while (0)
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#define firmware_restrict_branch_speculation_end() \
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do { \
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u64 val = x86_spec_ctrl_base; \
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\
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alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
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X86_FEATURE_USE_IBRS_FW); \
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preempt_enable(); \
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} while (0)
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DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
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DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
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DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
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#endif /* __ASSEMBLY__ */
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/*
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* Below is used in the eBPF JIT compiler and emits the byte sequence
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* for the following assembly:
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*
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* With retpolines configured:
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*
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* callq do_rop
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* spec_trap:
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* pause
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* lfence
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* jmp spec_trap
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* do_rop:
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* mov %rax,(%rsp) for x86_64
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* mov %edx,(%esp) for x86_32
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* retq
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*
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* Without retpolines configured:
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*
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* jmp *%rax for x86_64
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* jmp *%edx for x86_32
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*/
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#ifdef CONFIG_RETPOLINE
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# ifdef CONFIG_X86_64
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# define RETPOLINE_RAX_BPF_JIT_SIZE 17
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# define RETPOLINE_RAX_BPF_JIT() \
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do { \
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EMIT1_off32(0xE8, 7); /* callq do_rop */ \
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/* spec_trap: */ \
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EMIT2(0xF3, 0x90); /* pause */ \
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EMIT3(0x0F, 0xAE, 0xE8); /* lfence */ \
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EMIT2(0xEB, 0xF9); /* jmp spec_trap */ \
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/* do_rop: */ \
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EMIT4(0x48, 0x89, 0x04, 0x24); /* mov %rax,(%rsp) */ \
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EMIT1(0xC3); /* retq */ \
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} while (0)
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# else /* !CONFIG_X86_64 */
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# define RETPOLINE_EDX_BPF_JIT() \
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do { \
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EMIT1_off32(0xE8, 7); /* call do_rop */ \
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/* spec_trap: */ \
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EMIT2(0xF3, 0x90); /* pause */ \
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EMIT3(0x0F, 0xAE, 0xE8); /* lfence */ \
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EMIT2(0xEB, 0xF9); /* jmp spec_trap */ \
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/* do_rop: */ \
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EMIT3(0x89, 0x14, 0x24); /* mov %edx,(%esp) */ \
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EMIT1(0xC3); /* ret */ \
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} while (0)
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# endif
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#else /* !CONFIG_RETPOLINE */
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# ifdef CONFIG_X86_64
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# define RETPOLINE_RAX_BPF_JIT_SIZE 2
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# define RETPOLINE_RAX_BPF_JIT() \
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EMIT2(0xFF, 0xE0); /* jmp *%rax */
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# else /* !CONFIG_X86_64 */
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# define RETPOLINE_EDX_BPF_JIT() \
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EMIT2(0xFF, 0xE2) /* jmp *%edx */
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# endif
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#endif
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#endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
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