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13d52f6106
Currently sunxi_divs_clk_setup assumes the number of child clocks to be the same as the number of clock-output-names, and a maximum of SUNXI_DIVS_MAX_QTY child clocks. On sun6i, PLL6 only has 1 child clock, but the parent would be used as well, thereby also having it's own clock-output-names entry. This results in an extra bogus clock being registered. This patch adds an entry for the number of child clocks alongside the data structures for them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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.. | ||
clk-a10-hosc.c | ||
clk-a20-gmac.c | ||
clk-factors.c | ||
clk-factors.h | ||
clk-mod0.c | ||
clk-sun6i-apb0-gates.c | ||
clk-sun6i-apb0.c | ||
clk-sun6i-ar100.c | ||
clk-sun8i-apb0.c | ||
clk-sun8i-mbus.c | ||
clk-sun9i-core.c | ||
clk-sunxi.c | ||
Makefile |