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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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758d39ebd3
We have four different stack tracers of which three had bugs. So it's time to merge them to a single stack tracer which allows to specify a call back function which will be called for each step. This patch changes behavior a bit: - the "nosched" and "in_sched_functions" check within save_stack_trace_tsk did work only for the last stack frame within a context. Now it considers the check for each stack frame like it should. - both the oprofile variant and the perf_events variant did save a return address twice if a zero back chain was detected, which indicates an interrupt frame. The new dump_trace function will call the oprofile and perf_events backends with the psw address that is contained within the corresponding pt_regs structure instead. - the original show_trace and save_context_stack functions did already use the psw address of the pt_regs structure if a zero back chain was detected. However now we ignore the psw address if it is a user space address. After all we trace the kernel stack and not the user space stack. This way we also get rid of the garbage user space address in case of warnings and / or panic call traces. So this should make life easier since now there is only one stack tracer left which we can break. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
344 lines
8.6 KiB
C
344 lines
8.6 KiB
C
/*
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* S390 version
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* Copyright IBM Corp. 1999
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* Author(s): Hartmut Penner (hp@de.ibm.com),
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* Martin Schwidefsky (schwidefsky@de.ibm.com)
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*
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* Derived from "include/asm-i386/processor.h"
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* Copyright (C) 1994, Linus Torvalds
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*/
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#ifndef __ASM_S390_PROCESSOR_H
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#define __ASM_S390_PROCESSOR_H
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#include <linux/const.h>
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#define CIF_MCCK_PENDING 0 /* machine check handling is pending */
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#define CIF_ASCE 1 /* user asce needs fixup / uaccess */
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#define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
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#define CIF_FPU 3 /* restore FPU registers */
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#define CIF_IGNORE_IRQ 4 /* ignore interrupt (for udelay) */
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#define CIF_ENABLED_WAIT 5 /* in enabled wait state */
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#define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING)
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#define _CIF_ASCE _BITUL(CIF_ASCE)
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#define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY)
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#define _CIF_FPU _BITUL(CIF_FPU)
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#define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ)
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#define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT)
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#ifndef __ASSEMBLY__
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#include <linux/linkage.h>
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#include <linux/irqflags.h>
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#include <asm/cpu.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/setup.h>
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#include <asm/runtime_instr.h>
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#include <asm/fpu/types.h>
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#include <asm/fpu/internal.h>
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static inline void set_cpu_flag(int flag)
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{
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S390_lowcore.cpu_flags |= (1UL << flag);
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}
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static inline void clear_cpu_flag(int flag)
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{
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S390_lowcore.cpu_flags &= ~(1UL << flag);
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}
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static inline int test_cpu_flag(int flag)
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{
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return !!(S390_lowcore.cpu_flags & (1UL << flag));
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}
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/*
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* Test CIF flag of another CPU. The caller needs to ensure that
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* CPU hotplug can not happen, e.g. by disabling preemption.
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*/
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static inline int test_cpu_flag_of(int flag, int cpu)
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{
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struct lowcore *lc = lowcore_ptr[cpu];
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return !!(lc->cpu_flags & (1UL << flag));
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}
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#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
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static inline void get_cpu_id(struct cpuid *ptr)
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{
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asm volatile("stidp %0" : "=Q" (*ptr));
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}
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extern void s390_adjust_jiffies(void);
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extern const struct seq_operations cpuinfo_op;
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extern int sysctl_ieee_emulation_warnings;
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extern void execve_tail(void);
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/*
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* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
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*/
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#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
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#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
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(1UL << 30) : (1UL << 41))
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#define TASK_SIZE TASK_SIZE_OF(current)
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#define TASK_MAX_SIZE (1UL << 53)
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#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
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#define STACK_TOP_MAX (1UL << 42)
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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typedef struct {
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__u32 ar4;
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} mm_segment_t;
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/*
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* Thread structure
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*/
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struct thread_struct {
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struct fpu fpu; /* FP and VX register save area */
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unsigned int acrs[NUM_ACRS];
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unsigned long ksp; /* kernel stack pointer */
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mm_segment_t mm_segment;
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unsigned long gmap_addr; /* address of last gmap fault. */
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unsigned int gmap_pfault; /* signal of a pending guest pfault */
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struct per_regs per_user; /* User specified PER registers */
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struct per_event per_event; /* Cause of the last PER trap */
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unsigned long per_flags; /* Flags to control debug behavior */
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/* pfault_wait is used to block the process on a pfault event */
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unsigned long pfault_wait;
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struct list_head list;
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/* cpu runtime instrumentation */
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struct runtime_instr_cb *ri_cb;
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unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
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};
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/* Flag to disable transactions. */
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#define PER_FLAG_NO_TE 1UL
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/* Flag to enable random transaction aborts. */
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#define PER_FLAG_TE_ABORT_RAND 2UL
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/* Flag to specify random transaction abort mode:
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* - abort each transaction at a random instruction before TEND if set.
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* - abort random transactions at a random instruction if cleared.
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*/
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#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
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typedef struct thread_struct thread_struct;
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/*
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* Stack layout of a C stack frame.
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*/
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#ifndef __PACK_STACK
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struct stack_frame {
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unsigned long back_chain;
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unsigned long empty1[5];
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unsigned long gprs[10];
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unsigned int empty2[8];
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};
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#else
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struct stack_frame {
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unsigned long empty1[5];
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unsigned int empty2[8];
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unsigned long gprs[10];
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unsigned long back_chain;
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};
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#endif
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#define ARCH_MIN_TASKALIGN 8
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extern __vector128 init_task_fpu_regs[__NUM_VXRS];
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#define INIT_THREAD { \
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.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
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.fpu.regs = (void *)&init_task_fpu_regs, \
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}
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/*
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* Do necessary setup to start up a new thread.
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*/
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#define start_thread(regs, new_psw, new_stackp) do { \
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regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
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regs->psw.addr = new_psw; \
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regs->gprs[15] = new_stackp; \
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execve_tail(); \
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} while (0)
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#define start_thread31(regs, new_psw, new_stackp) do { \
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regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
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regs->psw.addr = new_psw; \
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regs->gprs[15] = new_stackp; \
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crst_table_downgrade(current->mm, 1UL << 31); \
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execve_tail(); \
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} while (0)
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/* Forward declaration, a strange C thing */
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struct task_struct;
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struct mm_struct;
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struct seq_file;
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typedef int (*dump_trace_func_t)(void *data, unsigned long address);
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void dump_trace(dump_trace_func_t func, void *data,
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struct task_struct *task, unsigned long sp);
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void show_cacheinfo(struct seq_file *m);
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/* Free all resources held by a thread. */
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extern void release_thread(struct task_struct *);
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/*
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* Return saved PC of a blocked thread.
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*/
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extern unsigned long thread_saved_pc(struct task_struct *t);
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unsigned long get_wchan(struct task_struct *p);
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#define task_pt_regs(tsk) ((struct pt_regs *) \
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(task_stack_page(tsk) + THREAD_SIZE) - 1)
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
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#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
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/* Has task runtime instrumentation enabled ? */
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#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
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static inline unsigned long current_stack_pointer(void)
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{
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unsigned long sp;
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asm volatile("la %0,0(15)" : "=a" (sp));
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return sp;
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}
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static inline unsigned short stap(void)
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{
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unsigned short cpu_address;
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asm volatile("stap %0" : "=m" (cpu_address));
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return cpu_address;
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}
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/*
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* Give up the time slice of the virtual PU.
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*/
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void cpu_relax(void);
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#define cpu_relax_lowlatency() barrier()
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static inline void psw_set_key(unsigned int key)
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{
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asm volatile("spka 0(%0)" : : "d" (key));
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}
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/*
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* Set PSW to specified value.
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*/
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static inline void __load_psw(psw_t psw)
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{
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asm volatile("lpswe %0" : : "Q" (psw) : "cc");
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}
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/*
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* Set PSW mask to specified value, while leaving the
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* PSW addr pointing to the next instruction.
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*/
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static inline void __load_psw_mask(unsigned long mask)
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{
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unsigned long addr;
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psw_t psw;
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psw.mask = mask;
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asm volatile(
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" larl %0,1f\n"
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" stg %0,%O1+8(%R1)\n"
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" lpswe %1\n"
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"1:"
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: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
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}
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/*
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* Extract current PSW mask
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*/
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static inline unsigned long __extract_psw(void)
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{
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unsigned int reg1, reg2;
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asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
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return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
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}
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static inline void local_mcck_enable(void)
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{
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__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
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}
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static inline void local_mcck_disable(void)
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{
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__load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
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}
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/*
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* Rewind PSW instruction address by specified number of bytes.
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*/
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static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
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{
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unsigned long mask;
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mask = (psw.mask & PSW_MASK_EA) ? -1UL :
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(psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
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(1UL << 24) - 1;
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return (psw.addr - ilc) & mask;
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}
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/*
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* Function to stop a processor until the next interrupt occurs
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*/
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void enabled_wait(void);
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/*
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* Function to drop a processor into disabled wait state
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*/
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static inline void __noreturn disabled_wait(unsigned long code)
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{
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psw_t psw;
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psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
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psw.addr = code;
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__load_psw(psw);
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while (1);
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}
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/*
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* Basic Machine Check/Program Check Handler.
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*/
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extern void s390_base_mcck_handler(void);
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extern void s390_base_pgm_handler(void);
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extern void s390_base_ext_handler(void);
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extern void (*s390_base_mcck_handler_fn)(void);
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extern void (*s390_base_pgm_handler_fn)(void);
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extern void (*s390_base_ext_handler_fn)(void);
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#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
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extern int memcpy_real(void *, void *, size_t);
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extern void memcpy_absolute(void *, void *, size_t);
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#define mem_assign_absolute(dest, val) { \
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__typeof__(dest) __tmp = (val); \
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\
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BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
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memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_S390_PROCESSOR_H */
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