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13bcb80b7e
linux_dsm_epyc7002/drivers/gpu
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Zhenyu Wang 13bcb80b7e drm/i915/gvt: Fix MI_FLUSH_DW parsing with correct index check 
When MI_FLUSH_DW post write hw status page in index mode, the index
value is in dword step and turned into address offset in cmd dword1.
As status page size is 4K, so can't exceed that.

This fixed upper bound check in cmd parser code which incorrectly
stopped VM for reason of invalid MI_FLUSH_DW write index.

v2:
- Fix upper bound as 4K page size because index value is address offset.

Fixes: be1da7070a ("drm/i915/gvt: vGPU command scanner")
Cc: stable@vger.kernel.org # v4.10+
Cc: "Zhao, Yan Y" <yan.y.zhao@intel.com>
Reviewed-by: Yan Zhao <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2019-02-21 12:19:19 +08:00
..
drm drm/i915/gvt: Fix MI_FLUSH_DW parsing with correct index check 2019-02-21 12:19:19 +08:00
host1x gpu: host1x: Add Tegra194 support 2018-11-29 17:11:49 +01:00
ipu-v3 gpu: ipu-v3: image-convert: allow three rows or columns 2018-11-05 14:40:08 +01:00
vga drm-misc-next for v4.21, part 1: 2018-11-19 10:40:33 +10:00
Makefile