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13ad1948d9
The code was setting the bit 21 of the CPCCR register to use a divider of 2 for the "pll half" clock, and clearing the bit to use a divider of 1. This is the opposite of how this register field works: a cleared bit means that the /2 divider is used, and a set bit means that the divider is 1. Restore the correct behaviour using the newly introduced .div_table field. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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| .. | ||
| cgu.c | ||
| cgu.h | ||
| jz4725b-cgu.c | ||
| jz4740-cgu.c | ||
| jz4770-cgu.c | ||
| jz4780-cgu.c | ||
| Kconfig | ||
| Makefile | ||