mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-03-11 23:27:42 +07:00
![]() The RM9200 USB clock is actually connected to a single parent (the PLLB) on which we can apply a specific divider. The USB clock divider does not allow for fine grained control on the USB clock frequency, hence propagating the set_rate request to the parent is the only choice we have to properly configure the USB clock rate. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reported-by: Gaël PORTAY <gael.portay@gmail.com> Tested-by: Gaël PORTAY <gael.portay@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> |
||
---|---|---|
.. | ||
clk-main.c | ||
clk-master.c | ||
clk-peripheral.c | ||
clk-pll.c | ||
clk-plldiv.c | ||
clk-programmable.c | ||
clk-slow.c | ||
clk-smd.c | ||
clk-system.c | ||
clk-usb.c | ||
clk-utmi.c | ||
Makefile | ||
pmc.c | ||
pmc.h | ||
sckc.c | ||
sckc.h |