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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
99baac21e4
Nadav reported parallel MADV_DONTNEED on same range has a stale TLB problem and Mel fixed it[1] and found same problem on MADV_FREE[2]. Quote from Mel Gorman: "The race in question is CPU 0 running madv_free and updating some PTEs while CPU 1 is also running madv_free and looking at the same PTEs. CPU 1 may have writable TLB entries for a page but fail the pte_dirty check (because CPU 0 has updated it already) and potentially fail to flush. Hence, when madv_free on CPU 1 returns, there are still potentially writable TLB entries and the underlying PTE is still present so that a subsequent write does not necessarily propagate the dirty bit to the underlying PTE any more. Reclaim at some unknown time at the future may then see that the PTE is still clean and discard the page even though a write has happened in the meantime. I think this is possible but I could have missed some protection in madv_free that prevents it happening." This patch aims for solving both problems all at once and is ready for other problem with KSM, MADV_FREE and soft-dirty story[3]. TLB batch API(tlb_[gather|finish]_mmu] uses [inc|dec]_tlb_flush_pending and mmu_tlb_flush_pending so that when tlb_finish_mmu is called, we can catch there are parallel threads going on. In that case, forcefully, flush TLB to prevent for user to access memory via stale TLB entry although it fail to gather page table entry. I confirmed this patch works with [4] test program Nadav gave so this patch supersedes "mm: Always flush VMA ranges affected by zap_page_range v2" in current mmotm. NOTE: This patch modifies arch-specific TLB gathering interface(x86, ia64, s390, sh, um). It seems most of architecture are straightforward but s390 need to be careful because tlb_flush_mmu works only if mm->context.flush_mm is set to non-zero which happens only a pte entry really is cleared by ptep_get_and_clear and friends. However, this problem never changes the pte entries but need to flush to prevent memory access from stale tlb. [1] http://lkml.kernel.org/r/20170725101230.5v7gvnjmcnkzzql3@techsingularity.net [2] http://lkml.kernel.org/r/20170725100722.2dxnmgypmwnrfawp@suse.de [3] http://lkml.kernel.org/r/BD3A0EBE-ECF4-41D4-87FA-C755EA9AB6BD@gmail.com [4] https://patchwork.kernel.org/patch/9861621/ [minchan@kernel.org: decrease tlb flush pending count in tlb_finish_mmu] Link: http://lkml.kernel.org/r/20170808080821.GA31730@bbox Link: http://lkml.kernel.org/r/20170802000818.4760-7-namit@vmware.com Signed-off-by: Minchan Kim <minchan@kernel.org> Signed-off-by: Nadav Amit <namit@vmware.com> Reported-by: Nadav Amit <namit@vmware.com> Reported-by: Mel Gorman <mgorman@techsingularity.net> Acked-by: Mel Gorman <mgorman@techsingularity.net> Cc: Ingo Molnar <mingo@redhat.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Tony Luck <tony.luck@intel.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Jeff Dike <jdike@addtoit.com> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Hugh Dickins <hughd@google.com> Cc: Mel Gorman <mgorman@suse.de> Cc: Nadav Amit <nadav.amit@gmail.com> Cc: Rik van Riel <riel@redhat.com> Cc: Sergey Senozhatsky <sergey.senozhatsky@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
169 lines
3.9 KiB
C
169 lines
3.9 KiB
C
#ifndef __ASM_SH_TLB_H
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#define __ASM_SH_TLB_H
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#ifdef CONFIG_SUPERH64
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# include <asm/tlb_64.h>
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#endif
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#ifndef __ASSEMBLY__
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#include <linux/pagemap.h>
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#ifdef CONFIG_MMU
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#include <linux/swap.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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/*
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* TLB handling. This allows us to remove pages from the page
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* tables, and efficiently handle the TLB issues.
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*/
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struct mmu_gather {
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struct mm_struct *mm;
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unsigned int fullmm;
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unsigned long start, end;
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};
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static inline void init_tlb_gather(struct mmu_gather *tlb)
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{
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tlb->start = TASK_SIZE;
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tlb->end = 0;
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if (tlb->fullmm) {
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tlb->start = 0;
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tlb->end = TASK_SIZE;
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}
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}
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static inline void
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arch_tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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tlb->mm = mm;
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tlb->start = start;
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tlb->end = end;
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tlb->fullmm = !(start | (end+1));
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init_tlb_gather(tlb);
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}
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static inline void
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arch_tlb_finish_mmu(struct mmu_gather *tlb,
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unsigned long start, unsigned long end, bool force)
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{
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if (tlb->fullmm || force)
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flush_tlb_mm(tlb->mm);
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/* keep the page table cache within bounds */
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check_pgt_cache();
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}
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static inline void
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tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long address)
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{
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if (tlb->start > address)
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tlb->start = address;
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if (tlb->end < address + PAGE_SIZE)
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tlb->end = address + PAGE_SIZE;
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}
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#define tlb_remove_huge_tlb_entry(h, tlb, ptep, address) \
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tlb_remove_tlb_entry(tlb, ptep, address)
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/*
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* In the case of tlb vma handling, we can optimise these away in the
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* case where we're doing a full MM flush. When we're doing a munmap,
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* the vmas are adjusted to only cover the region to be torn down.
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*/
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static inline void
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tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
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{
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if (!tlb->fullmm)
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flush_cache_range(vma, vma->vm_start, vma->vm_end);
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}
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static inline void
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tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
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{
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if (!tlb->fullmm && tlb->end) {
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flush_tlb_range(vma, tlb->start, tlb->end);
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init_tlb_gather(tlb);
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}
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}
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static inline void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb)
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{
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}
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static inline void tlb_flush_mmu_free(struct mmu_gather *tlb)
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{
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}
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static inline void tlb_flush_mmu(struct mmu_gather *tlb)
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{
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}
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static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
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{
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free_page_and_swap_cache(page);
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return false; /* avoid calling tlb_flush_mmu */
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}
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static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
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{
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__tlb_remove_page(tlb, page);
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}
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static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
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struct page *page, int page_size)
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{
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return __tlb_remove_page(tlb, page);
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}
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static inline void tlb_remove_page_size(struct mmu_gather *tlb,
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struct page *page, int page_size)
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{
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return tlb_remove_page(tlb, page);
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}
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#define tlb_remove_check_page_size_change tlb_remove_check_page_size_change
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static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb,
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unsigned int page_size)
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{
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}
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#define pte_free_tlb(tlb, ptep, addr) pte_free((tlb)->mm, ptep)
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#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp)
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#define pud_free_tlb(tlb, pudp, addr) pud_free((tlb)->mm, pudp)
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#define tlb_migrate_finish(mm) do { } while (0)
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#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SUPERH64)
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extern void tlb_wire_entry(struct vm_area_struct *, unsigned long, pte_t);
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extern void tlb_unwire_entry(void);
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#else
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static inline void tlb_wire_entry(struct vm_area_struct *vma ,
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unsigned long addr, pte_t pte)
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{
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BUG();
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}
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static inline void tlb_unwire_entry(void)
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{
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BUG();
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}
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#endif
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#else /* CONFIG_MMU */
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#define tlb_start_vma(tlb, vma) do { } while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
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#define tlb_flush(tlb) do { } while (0)
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#include <asm-generic/tlb.h>
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#endif /* CONFIG_MMU */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_SH_TLB_H */
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