mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
1db823ee9f
The glue around the core designware IP is significantly different between the Exynos and i.MX implementation, which is reflected in the DT bindings. This changes the i.MX6 binding to reuse as much as possible from the common designware binding and removes old cruft. I removed the optional GPIOs with the following reasoning: - disable-gpio: endpoint specific GPIO, not currently wired up in any code. Should be handled by the PCI device driver, not the host controller driver. - wake-up-gpio: same as above. - power-on-gpio: No user in any upstream DT. This should be handled by a regulator which shouldn't be controlled by the host driver, but rather by the PCI device driver. [bhelgaas: whitespace fixes] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
22 lines
717 B
Plaintext
22 lines
717 B
Plaintext
* Synopsys Designware PCIe interface
|
|
|
|
Required properties:
|
|
- compatible: should contain "snps,dw-pcie" to identify the core.
|
|
- #address-cells: set to <3>
|
|
- #size-cells: set to <2>
|
|
- device_type: set to "pci"
|
|
- ranges: ranges for the PCI memory and I/O regions
|
|
- #interrupt-cells: set to <1>
|
|
- interrupt-map-mask and interrupt-map: standard PCI properties
|
|
to define the mapping of the PCIe interface to interrupt
|
|
numbers.
|
|
- num-lanes: number of lanes to use
|
|
- clocks: Must contain an entry for each entry in clock-names.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: Must include the following entries:
|
|
- "pcie"
|
|
- "pcie_bus"
|
|
|
|
Optional properties:
|
|
- reset-gpio: gpio pin number of power good signal
|