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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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eab4002660
This tag contains the patches I'd like to target for 5.7. It has a handful of new features: * Partial support for the Kendryte K210. There are still a few outstanding issues that I have patches for, but I don't actually have a board to test them so they're not included yet. * SBI v0.2 support. * Fixes to support for building with LLVM-based toolchains. The resulting images are known not to boot yet. This builds and boots for me. There is one merge conflict, it's just a Kconfig merge issue. I can publish a resolved branch if you'd like. I don't anticipate a part two, but I'll probably have something early in the RCs to finish up the K210 support. -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAl6OAAoTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiUqKEACidkNwwFf10hN6ojnIsBeh0mvZ0QuD qw5Uj0L5rmKdf84IRUGH8A3tyal39BoNz41Eo0mvZoInj542fVMArrqpAIKHN6e+ GMOoHgeZO329zQYMqBX1RN/W9MV80KPKZcROeWkL+AbAmbQBaVRq08Ur1QIg2bHI 84H0LzlCd1xz9k827ypOyz7ix4OYkli7DcUgdiPTK95CjaseALQXvSYA237lcXpB 3g2L+/TDrjtGHn+vy3XWLJISY/BY4ZKfWN0UL4CJHvGuL61tJ+VRXaA3DQcBNd56 7du41GTz9BU6J5wZTVnB5HstebwiXyP8pY34Pp8S4/wWyVdoi5hZ0Jn7sC9oDdnA r/CjawrGCZv6IEt69YA1edo3AoR13gXCbylRovdxVMRYa0OLmcTfFr843svTZzbQ ECSt6te2J2YwtYeLO6AlZeu2gBLW0Mxh5JBmiB8sy9C8tVlD/EFTYrnhEQnjUEVx wV76wfbeYL1be5IS4Tu/d0F5My6miIL+JafUND0bJQ7igp08po/YY4NIg/xyYlM2 Aqie3MuTYlA3/I20N1K2mQkQnjKS4Y5AqNDj5povew2mPUvTGuLhZDZ/asKxdBIf BSq3V74V/Vc+qsh1d5IhUCDVthGYqBoJoBSUjcbItrpgmhLyvhbbSCLeF8ehDPeI Y9074bg5YH79pg== =P1DO -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: "This contains a handful of new features: - Partial support for the Kendryte K210. There are still a few outstanding issues that I have patches for, but I don't actually have a board to test them so they're not included yet. - SBI v0.2 support. - Fixes to support for building with LLVM-based toolchains. The resulting images are known not to boot yet. I don't anticipate a part two, but I'll probably have something early in the RCs to finish up the K210 support" * tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits) riscv: create a loader.bin boot image for Kendryte SoC riscv: Kendryte K210 default config riscv: Add Kendryte K210 device tree riscv: Select required drivers for Kendryte SOC riscv: Add Kendryte K210 SoC support riscv: Add SOC early init support riscv: Unaligned load/store handling for M_MODE RISC-V: Support cpu hotplug RISC-V: Add supported for ordered booting method using HSM RISC-V: Add SBI HSM extension definitions RISC-V: Export SBI error to linux error mapping function RISC-V: Add cpu_ops and modify default booting method RISC-V: Move relocate and few other functions out of __init RISC-V: Implement new SBI v0.2 extensions RISC-V: Introduce a new config for SBI v0.1 RISC-V: Add SBI v0.2 extension definitions RISC-V: Add basic support for SBI v0.2 RISC-V: Mark existing SBI as 0.1 SBI. riscv: Use macro definition instead of magic number riscv: Add support to dump the kernel page tables ...
184 lines
4.7 KiB
C
184 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#include <linux/cpu.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/sched/debug.h>
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#include <linux/sched/signal.h>
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#include <linux/signal.h>
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#include <linux/kdebug.h>
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#include <linux/uaccess.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/csr.h>
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int show_unhandled_signals = 1;
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extern asmlinkage void handle_exception(void);
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static DEFINE_SPINLOCK(die_lock);
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void die(struct pt_regs *regs, const char *str)
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{
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static int die_counter;
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int ret;
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oops_enter();
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spin_lock_irq(&die_lock);
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console_verbose();
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bust_spinlocks(1);
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pr_emerg("%s [#%d]\n", str, ++die_counter);
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print_modules();
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show_regs(regs);
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ret = notify_die(DIE_OOPS, str, regs, 0, regs->cause, SIGSEGV);
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bust_spinlocks(0);
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add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
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spin_unlock_irq(&die_lock);
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oops_exit();
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if (in_interrupt())
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panic("Fatal exception in interrupt");
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if (panic_on_oops)
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panic("Fatal exception");
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if (ret != NOTIFY_STOP)
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do_exit(SIGSEGV);
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}
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void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr)
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{
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struct task_struct *tsk = current;
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if (show_unhandled_signals && unhandled_signal(tsk, signo)
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&& printk_ratelimit()) {
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pr_info("%s[%d]: unhandled signal %d code 0x%x at 0x" REG_FMT,
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tsk->comm, task_pid_nr(tsk), signo, code, addr);
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print_vma_addr(KERN_CONT " in ", instruction_pointer(regs));
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pr_cont("\n");
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show_regs(regs);
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}
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force_sig_fault(signo, code, (void __user *)addr);
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}
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static void do_trap_error(struct pt_regs *regs, int signo, int code,
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unsigned long addr, const char *str)
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{
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if (user_mode(regs)) {
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do_trap(regs, signo, code, addr);
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} else {
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if (!fixup_exception(regs))
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die(regs, str);
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}
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}
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#define DO_ERROR_INFO(name, signo, code, str) \
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asmlinkage __visible void name(struct pt_regs *regs) \
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{ \
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do_trap_error(regs, signo, code, regs->epc, "Oops - " str); \
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}
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DO_ERROR_INFO(do_trap_unknown,
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SIGILL, ILL_ILLTRP, "unknown exception");
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DO_ERROR_INFO(do_trap_insn_misaligned,
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SIGBUS, BUS_ADRALN, "instruction address misaligned");
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DO_ERROR_INFO(do_trap_insn_fault,
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SIGSEGV, SEGV_ACCERR, "instruction access fault");
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DO_ERROR_INFO(do_trap_insn_illegal,
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SIGILL, ILL_ILLOPC, "illegal instruction");
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DO_ERROR_INFO(do_trap_load_fault,
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SIGSEGV, SEGV_ACCERR, "load access fault");
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#ifndef CONFIG_RISCV_M_MODE
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DO_ERROR_INFO(do_trap_load_misaligned,
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SIGBUS, BUS_ADRALN, "Oops - load address misaligned");
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DO_ERROR_INFO(do_trap_store_misaligned,
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SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned");
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#else
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int handle_misaligned_load(struct pt_regs *regs);
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int handle_misaligned_store(struct pt_regs *regs);
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asmlinkage void do_trap_load_misaligned(struct pt_regs *regs)
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{
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if (!handle_misaligned_load(regs))
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return;
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do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
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"Oops - load address misaligned");
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}
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asmlinkage void do_trap_store_misaligned(struct pt_regs *regs)
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{
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if (!handle_misaligned_store(regs))
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return;
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do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
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"Oops - store (or AMO) address misaligned");
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}
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#endif
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DO_ERROR_INFO(do_trap_store_fault,
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SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault");
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DO_ERROR_INFO(do_trap_ecall_u,
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SIGILL, ILL_ILLTRP, "environment call from U-mode");
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DO_ERROR_INFO(do_trap_ecall_s,
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SIGILL, ILL_ILLTRP, "environment call from S-mode");
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DO_ERROR_INFO(do_trap_ecall_m,
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SIGILL, ILL_ILLTRP, "environment call from M-mode");
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static inline unsigned long get_break_insn_length(unsigned long pc)
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{
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bug_insn_t insn;
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if (probe_kernel_address((bug_insn_t *)pc, insn))
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return 0;
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return GET_INSN_LENGTH(insn);
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}
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asmlinkage __visible void do_trap_break(struct pt_regs *regs)
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{
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if (user_mode(regs))
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force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->epc);
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else if (report_bug(regs->epc, regs) == BUG_TRAP_TYPE_WARN)
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regs->epc += get_break_insn_length(regs->epc);
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else
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die(regs, "Kernel BUG");
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}
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#ifdef CONFIG_GENERIC_BUG
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int is_valid_bugaddr(unsigned long pc)
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{
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bug_insn_t insn;
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if (pc < VMALLOC_START)
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return 0;
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if (probe_kernel_address((bug_insn_t *)pc, insn))
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return 0;
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if ((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32)
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return (insn == __BUG_INSN_32);
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else
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return ((insn & __COMPRESSED_INSN_MASK) == __BUG_INSN_16);
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}
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#endif /* CONFIG_GENERIC_BUG */
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void trap_init(void)
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{
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/*
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* Set sup0 scratch register to 0, indicating to exception vector
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* that we are presently executing in the kernel
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*/
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csr_write(CSR_SCRATCH, 0);
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/* Set the exception vector address */
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csr_write(CSR_TVEC, &handle_exception);
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/* Enable interrupts */
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csr_write(CSR_IE, IE_SIE);
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}
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