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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7f38839628
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (47 commits) Blackfin: bfin_spi.h: add MMR peripheral layout Blackfin: bfin_ppi.h: start a common PPI/EPPI header Blackfin: bfin_can.h: add missing VERSION/VERSION2 MMRs Blackfin: bf538: add missing SIC_RVECT define Blackfin: bf561: rewrite SICA_xxx to just SIC_xxx Blackfin: bf54x: add missing SIC_RVECT definition Blackfin: H8606: move 8250 irqflags to platform resources Blackfin: glue XIP/ROM kernel kconfigs Blackfin: update sparse flags for latest upstream changes Blackfin: coreb: update ioctl numbers Blackfin: coreb: add gpl module license Blackfin: bf518-ezkit: add ssm2603 codec resources Blackfin: bf51x/bf52x: fix 16/32bit SPORT MMR helpers Blackfin: tll6527m: new board port Blackfin: bf526-ezbrd/bf527-ezkit: add NAND partition for u-boot Blackfin: merge kernel init memory back into main memory region Blackfin: gpio: add peripheral group check Blackfin: dma: bf54x: add missing break for SPORT1 TX IRQ Blackfin: add new cacheflush syscall Blackfin: bf548-ezkit: increase u-boot partition size ...
78 lines
1.9 KiB
C
78 lines
1.9 KiB
C
/* Load firmware into Core B on a BF561
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* The Core B reset func requires code in the application that is loaded into
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* Core B. In order to reset, the application needs to install an interrupt
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* handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and
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* writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core
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* B to stall when Supplemental Interrupt 0 is set, and will reset PC to
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* 0xff600000 when COREB_SRAM_INIT is cleared.
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*/
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#include <linux/device.h>
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#include <linux/fs.h>
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#include <linux/kernel.h>
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#include <linux/miscdevice.h>
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#include <linux/module.h>
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#define CMD_COREB_START _IO('b', 0)
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#define CMD_COREB_STOP _IO('b', 1)
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#define CMD_COREB_RESET _IO('b', 2)
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static long
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coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
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{
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int ret = 0;
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switch (cmd) {
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case CMD_COREB_START:
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bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
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break;
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case CMD_COREB_STOP:
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bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
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break;
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case CMD_COREB_RESET:
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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CSYNC();
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return ret;
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}
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static const struct file_operations coreb_fops = {
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.owner = THIS_MODULE,
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.unlocked_ioctl = coreb_ioctl,
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.llseek = noop_llseek,
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};
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static struct miscdevice coreb_dev = {
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.minor = MISC_DYNAMIC_MINOR,
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.name = "coreb",
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.fops = &coreb_fops,
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};
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static int __init bf561_coreb_init(void)
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{
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return misc_register(&coreb_dev);
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}
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module_init(bf561_coreb_init);
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static void __exit bf561_coreb_exit(void)
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{
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misc_deregister(&coreb_dev);
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}
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module_exit(bf561_coreb_exit);
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MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");
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MODULE_DESCRIPTION("BF561 Core B Support");
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MODULE_LICENSE("GPL");
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