mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 07:36:44 +07:00
a29ef819f3
According to the imx27 documentation, fec has a 4 Kbyte
memory space map. Moreover, the actual 16 Kbyte mapping
overlaps the SCC (Security Controller) memory register
space. So, we reduce the memory register space to 4 Kbyte.
Signed-off-by: Philippe Reynes <tremyfr@gmail.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Fixes: 9f0749e3eb ("ARM i.MX27: Add devicetree support")
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
578 lines
14 KiB
Plaintext
578 lines
14 KiB
Plaintext
/*
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* Copyright 2012 Sascha Hauer, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "skeleton.dtsi"
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#include "imx27-pinfunc.h"
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#include <dt-bindings/clock/imx27-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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aliases {
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ethernet0 = &fec;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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spi0 = &cspi1;
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spi1 = &cspi2;
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spi2 = &cspi3;
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};
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aitc: aitc-interrupt-controller@e0000000 {
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compatible = "fsl,imx27-aitc", "fsl,avic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x10040000 0x1000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc26m {
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compatible = "fsl,imx-osc26m", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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};
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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operating-points = <
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/* kHz uV */
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266000 1300000
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399000 1450000
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>;
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clock-latency = <62500>;
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clocks = <&clks IMX27_CLK_CPU_DIV>;
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voltage-tolerance = <5>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&aitc>;
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ranges;
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aipi@10000000 { /* AIPI1 */
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10000000 0x20000>;
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ranges;
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dma: dma@10001000 {
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compatible = "fsl,imx27-dma";
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reg = <0x10001000 0x1000>;
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interrupts = <32>;
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clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
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<&clks IMX27_CLK_DMA_AHB_GATE>;
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clock-names = "ipg", "ahb";
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#dma-cells = <1>;
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#dma-channels = <16>;
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};
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wdog: wdog@10002000 {
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compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
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reg = <0x10002000 0x1000>;
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interrupts = <27>;
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clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
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};
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gpt1: timer@10003000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x10003000 0x1000>;
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interrupts = <26>;
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clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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gpt2: timer@10004000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x10004000 0x1000>;
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interrupts = <25>;
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clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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gpt3: timer@10005000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x10005000 0x1000>;
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interrupts = <24>;
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clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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pwm: pwm@10006000 {
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#pwm-cells = <2>;
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compatible = "fsl,imx27-pwm";
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reg = <0x10006000 0x1000>;
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interrupts = <23>;
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clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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kpp: kpp@10008000 {
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compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
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reg = <0x10008000 0x1000>;
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interrupts = <21>;
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clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
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status = "disabled";
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};
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owire: owire@10009000 {
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compatible = "fsl,imx27-owire", "fsl,imx21-owire";
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reg = <0x10009000 0x1000>;
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clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
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status = "disabled";
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart2: serial@1000b000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000b000 0x1000>;
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interrupts = <19>;
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clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart3: serial@1000c000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000c000 0x1000>;
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interrupts = <18>;
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clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart4: serial@1000d000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000d000 0x1000>;
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interrupts = <17>;
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clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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cspi1: cspi@1000e000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x1000e000 0x1000>;
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interrupts = <16>;
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clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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cspi2: cspi@1000f000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x1000f000 0x1000>;
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interrupts = <15>;
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clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ssi1: ssi@10010000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
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reg = <0x10010000 0x1000>;
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interrupts = <14>;
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clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
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dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
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dma-names = "rx0", "tx0", "rx1", "tx1";
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fsl,fifo-depth = <8>;
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status = "disabled";
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};
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ssi2: ssi@10011000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
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reg = <0x10011000 0x1000>;
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interrupts = <13>;
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clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
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dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
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dma-names = "rx0", "tx0", "rx1", "tx1";
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fsl,fifo-depth = <8>;
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status = "disabled";
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};
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i2c1: i2c@10012000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
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reg = <0x10012000 0x1000>;
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interrupts = <12>;
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clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
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status = "disabled";
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};
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sdhci1: sdhci@10013000 {
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compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
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reg = <0x10013000 0x1000>;
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interrupts = <11>;
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clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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dmas = <&dma 7>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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sdhci2: sdhci@10014000 {
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compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
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reg = <0x10014000 0x1000>;
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interrupts = <10>;
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clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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dmas = <&dma 6>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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iomuxc: iomuxc@10015000 {
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compatible = "fsl,imx27-iomuxc";
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reg = <0x10015000 0x600>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio1: gpio@10015000 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015000 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@10015100 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015100 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@10015200 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015200 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@10015300 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015300 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@10015400 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015400 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio@10015500 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015500 0x100>;
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clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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audmux: audmux@10016000 {
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compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
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reg = <0x10016000 0x1000>;
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clocks = <&clks IMX27_CLK_DUMMY>;
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clock-names = "audmux";
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status = "disabled";
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};
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cspi3: cspi@10017000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x10017000 0x1000>;
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interrupts = <6>;
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clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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gpt4: timer@10019000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x10019000 0x1000>;
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interrupts = <4>;
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clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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gpt5: timer@1001a000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x1001a000 0x1000>;
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interrupts = <3>;
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clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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uart5: serial@1001b000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1001b000 0x1000>;
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interrupts = <49>;
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clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart6: serial@1001c000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1001c000 0x1000>;
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interrupts = <48>;
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clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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i2c2: i2c@1001d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
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reg = <0x1001d000 0x1000>;
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interrupts = <1>;
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clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
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status = "disabled";
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};
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sdhci3: sdhci@1001e000 {
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compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
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reg = <0x1001e000 0x1000>;
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interrupts = <9>;
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clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
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<&clks IMX27_CLK_PER2_GATE>;
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clock-names = "ipg", "per";
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dmas = <&dma 36>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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gpt6: timer@1001f000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x1001f000 0x1000>;
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interrupts = <2>;
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clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
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<&clks IMX27_CLK_PER1_GATE>;
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clock-names = "ipg", "per";
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};
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};
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aipi@10020000 { /* AIPI2 */
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10020000 0x20000>;
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ranges;
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fb: fb@10021000 {
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compatible = "fsl,imx27-fb", "fsl,imx21-fb";
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interrupts = <61>;
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reg = <0x10021000 0x1000>;
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clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
|
|
<&clks IMX27_CLK_LCDC_AHB_GATE>,
|
|
<&clks IMX27_CLK_PER3_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
coda: coda@10023000 {
|
|
compatible = "fsl,imx27-vpu", "cnm,codadx6";
|
|
reg = <0x10023000 0x0200>;
|
|
interrupts = <53>;
|
|
clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
|
|
<&clks IMX27_CLK_VPU_AHB_GATE>;
|
|
clock-names = "per", "ahb";
|
|
iram = <&iram>;
|
|
};
|
|
|
|
usbotg: usb@10024000 {
|
|
compatible = "fsl,imx27-usb";
|
|
reg = <0x10024000 0x200>;
|
|
interrupts = <56>;
|
|
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh1: usb@10024200 {
|
|
compatible = "fsl,imx27-usb";
|
|
reg = <0x10024200 0x200>;
|
|
interrupts = <54>;
|
|
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
|
fsl,usbmisc = <&usbmisc 1>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh2: usb@10024400 {
|
|
compatible = "fsl,imx27-usb";
|
|
reg = <0x10024400 0x200>;
|
|
interrupts = <55>;
|
|
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
|
|
fsl,usbmisc = <&usbmisc 2>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc: usbmisc@10024600 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx27-usbmisc";
|
|
reg = <0x10024600 0x200>;
|
|
clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
|
|
};
|
|
|
|
sahara2: sahara@10025000 {
|
|
compatible = "fsl,imx27-sahara";
|
|
reg = <0x10025000 0x1000>;
|
|
interrupts = <59>;
|
|
clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
|
|
<&clks IMX27_CLK_SAHARA_AHB_GATE>;
|
|
clock-names = "ipg", "ahb";
|
|
};
|
|
|
|
clks: ccm@10027000{
|
|
compatible = "fsl,imx27-ccm";
|
|
reg = <0x10027000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
iim: iim@10028000 {
|
|
compatible = "fsl,imx27-iim";
|
|
reg = <0x10028000 0x1000>;
|
|
interrupts = <62>;
|
|
clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
|
|
};
|
|
|
|
fec: ethernet@1002b000 {
|
|
compatible = "fsl,imx27-fec";
|
|
reg = <0x1002b000 0x1000>;
|
|
interrupts = <50>;
|
|
clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
|
|
<&clks IMX27_CLK_FEC_AHB_GATE>;
|
|
clock-names = "ipg", "ahb";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
nfc: nand@d8000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,imx27-nand";
|
|
reg = <0xd8000000 0x1000>;
|
|
interrupts = <29>;
|
|
clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
weim: weim@d8002000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,imx27-weim";
|
|
reg = <0xd8002000 0x1000>;
|
|
clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
|
|
ranges = <
|
|
0 0 0xc0000000 0x08000000
|
|
1 0 0xc8000000 0x08000000
|
|
2 0 0xd0000000 0x02000000
|
|
3 0 0xd2000000 0x02000000
|
|
4 0 0xd4000000 0x02000000
|
|
5 0 0xd6000000 0x02000000
|
|
>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iram: iram@ffff4c00 {
|
|
compatible = "mmio-sram";
|
|
reg = <0xffff4c00 0xb400>;
|
|
};
|
|
};
|
|
};
|