mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 01:36:44 +07:00
c553138fbd
Instead of __raw_*, define imx_* to *_relaxed and use those. Using imx_* was requested by Arnd because *_relaxed tends to indicate that the code was carefully reviewed to not require any synchronisation and otherwise be safe, which isn't the case here with the automatic conversion. The conversion itself was done using the following spatch (since that automatically adjusts the coding style unlike a simple search&replace). @@ expression E1, E2; @@ -__raw_writel(E1, E2) +imx_writel(E1, E2) @@ expression E1, E2; @@ -__raw_writew(E1, E2) +imx_writew(E1, E2) @@ expression E1; @@ -__raw_readl(E1) +imx_readl(E1) @@ expression E1; @@ -__raw_readw(E1) +imx_readw(E1) Signed-off-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/*
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* MX31 CPU type detection
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*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include "common.h"
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#include "hardware.h"
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#include "iim.h"
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static int mx31_cpu_rev = -1;
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static struct {
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u8 srev;
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const char *name;
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unsigned int rev;
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} mx31_cpu_type[] = {
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{ .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
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{ .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
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{ .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
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{ .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
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{ .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
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{ .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 },
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{ .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 },
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{ .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 },
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{ .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 },
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};
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static int mx31_read_cpu_rev(void)
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{
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u32 i, srev;
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/* read SREV register from IIM module */
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srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
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srev &= 0xff;
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for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
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if (srev == mx31_cpu_type[i].srev) {
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imx_print_silicon_rev(mx31_cpu_type[i].name,
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mx31_cpu_type[i].rev);
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return mx31_cpu_type[i].rev;
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}
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imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
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return IMX_CHIP_REVISION_UNKNOWN;
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}
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int mx31_revision(void)
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{
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if (mx31_cpu_rev == -1)
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mx31_cpu_rev = mx31_read_cpu_rev();
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return mx31_cpu_rev;
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}
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EXPORT_SYMBOL(mx31_revision);
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