mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-25 06:49:40 +07:00
d07706276b
I missed the fact that these constants was not yet available, so hard code their values in the dts to make the branch compile on its own. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
868 lines
20 KiB
Plaintext
868 lines
20 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2019, Linaro Limited
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-aoss-qmp.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,gcc-sm8150.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32764>;
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clock-output-names = "sleep_clk";
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_0: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_100: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_200>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_200: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_300>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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L2_300: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_400>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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L2_400: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_500>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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L2_500: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_600>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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L2_600: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo485";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_700>;
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qcom,freq-domain = <&cpufreq_hw 2>;
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L2_700: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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};
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firmware {
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scm: scm {
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compatible = "qcom,scm-sm8150", "qcom,scm";
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#reset-cells = <1>;
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};
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x1000>;
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#hwlock-cells = <1>;
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: memory@85700000 {
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reg = <0x0 0x85700000 0x0 0x600000>;
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no-map;
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};
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xbl_mem: memory@85d00000 {
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reg = <0x0 0x85d00000 0x0 0x140000>;
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no-map;
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};
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aop_mem: memory@85f00000 {
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reg = <0x0 0x85f00000 0x0 0x20000>;
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no-map;
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};
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aop_cmd_db: memory@85f20000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x85f20000 0x0 0x20000>;
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no-map;
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};
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smem_mem: memory@86000000 {
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reg = <0x0 0x86000000 0x0 0x200000>;
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no-map;
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};
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tz_mem: memory@86200000 {
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reg = <0x0 0x86200000 0x0 0x3900000>;
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no-map;
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};
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rmtfs_mem: memory@89b00000 {
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compatible = "qcom,rmtfs-mem";
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reg = <0x0 0x89b00000 0x0 0x200000>;
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no-map;
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qcom,client-id = <1>;
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qcom,vmid = <15>;
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};
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camera_mem: memory@8b700000 {
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reg = <0x0 0x8b700000 0x0 0x500000>;
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no-map;
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};
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wlan_mem: memory@8bc00000 {
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reg = <0x0 0x8bc00000 0x0 0x180000>;
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no-map;
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};
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npu_mem: memory@8bd80000 {
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reg = <0x0 0x8bd80000 0x0 0x80000>;
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no-map;
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};
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adsp_mem: memory@8be00000 {
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reg = <0x0 0x8be00000 0x0 0x1a00000>;
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no-map;
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};
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mpss_mem: memory@8d800000 {
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reg = <0x0 0x8d800000 0x0 0x9600000>;
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no-map;
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};
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venus_mem: memory@96e00000 {
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reg = <0x0 0x96e00000 0x0 0x500000>;
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no-map;
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};
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slpi_mem: memory@97300000 {
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reg = <0x0 0x97300000 0x0 0x1400000>;
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no-map;
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};
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ipa_fw_mem: memory@98700000 {
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reg = <0x0 0x98700000 0x0 0x10000>;
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no-map;
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};
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ipa_gsi_mem: memory@98710000 {
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reg = <0x0 0x98710000 0x0 0x5000>;
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no-map;
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};
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gpu_mem: memory@98715000 {
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reg = <0x0 0x98715000 0x0 0x2000>;
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no-map;
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};
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spss_mem: memory@98800000 {
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reg = <0x0 0x98800000 0x0 0x100000>;
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no-map;
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};
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cdsp_mem: memory@98900000 {
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reg = <0x0 0x98900000 0x0 0x1400000>;
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no-map;
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};
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qseecom_mem: memory@9e400000 {
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reg = <0x0 0x9e400000 0x0 0x1400000>;
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no-map;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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smp2p-cdsp {
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compatible = "qcom,smp2p";
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qcom,smem = <94>, <432>;
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interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apss_shared 6>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <5>;
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cdsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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cdsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-lpass {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apss_shared 10>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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adsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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adsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-mpss {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apss_shared 14>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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modem_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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modem_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-slpi {
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compatible = "qcom,smp2p";
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qcom,smem = <481>, <430>;
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interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apss_shared 26>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <3>;
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slpi_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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slpi_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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dma-ranges = <0 0 0 0 0x10 0>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sm8150";
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reg = <0x0 0x00100000 0x0 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clock-names = "bi_tcxo",
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"sleep_clk";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>;
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};
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qupv3_id_1: geniqup@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x00ac0000 0x0 0x6000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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uart2: serial@a90000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x0 0x00a90000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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ufs_mem_hc: ufshc@1d84000 {
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compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
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"jedec,ufs-2.0";
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reg = <0 0x01d84000 0 0x2500>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs_mem_phy_lanes>;
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phy-names = "ufsphy";
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lanes-per-direction = <2>;
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#reset-cells = <1>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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freq-table-hz =
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>;
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status = "disabled";
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};
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ufs_mem_phy: phy@1d87000 {
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compatible = "qcom,sm8150-qmp-ufs-phy";
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reg = <0 0x01d87000 0 0x1c0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clock-names = "ref",
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"ref_aux";
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clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
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resets = <&ufs_mem_hc 0>;
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reset-names = "ufsphy";
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status = "disabled";
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ufs_mem_phy_lanes: lanes@1d87400 {
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reg = <0 0x01d87400 0 0x108>,
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<0 0x01d87600 0 0x1e0>,
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<0 0x01d87c00 0 0x1dc>,
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<0 0x01d87800 0 0x108>,
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<0 0x01d87a00 0 0x1e0>;
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#phy-cells = <0>;
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};
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};
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tcsr_mutex_regs: syscon@1f40000 {
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compatible = "syscon";
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reg = <0x0 0x01f40000 0x0 0x40000>;
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};
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remoteproc_slpi: remoteproc@2400000 {
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compatible = "qcom,sm8150-slpi-pas";
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reg = <0x0 0x02400000 0x0 0x4040>;
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interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
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<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
|
|
<&rpmhpd 3>,
|
|
<&rpmhpd 2>;
|
|
power-domain-names = "load_state", "lcx", "lmx";
|
|
|
|
memory-region = <&slpi_mem>;
|
|
|
|
qcom,smem-states = <&slpi_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
|
|
label = "dsps";
|
|
qcom,remote-pid = <3>;
|
|
mboxes = <&apss_shared 24>;
|
|
};
|
|
};
|
|
|
|
tlmm: pinctrl@3100000 {
|
|
compatible = "qcom,sm8150-pinctrl";
|
|
reg = <0x0 0x03100000 0x0 0x300000>,
|
|
<0x0 0x03500000 0x0 0x300000>,
|
|
<0x0 0x03900000 0x0 0x300000>,
|
|
<0x0 0x03D00000 0x0 0x300000>;
|
|
reg-names = "west", "east", "north", "south";
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-ranges = <&tlmm 0 0 175>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
remoteproc_mpss: remoteproc@4080000 {
|
|
compatible = "qcom,sm8150-mpss-pas";
|
|
reg = <0x0 0x04080000 0x0 0x4040>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
|
|
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
|
|
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready", "handover",
|
|
"stop-ack", "shutdown-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
|
|
<&rpmhpd 7>,
|
|
<&rpmhpd 0>;
|
|
power-domain-names = "load_state", "cx", "mss";
|
|
|
|
memory-region = <&mpss_mem>;
|
|
|
|
qcom,smem-states = <&modem_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
glink-edge {
|
|
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
|
|
label = "modem";
|
|
qcom,remote-pid = <1>;
|
|
mboxes = <&apss_shared 12>;
|
|
};
|
|
};
|
|
|
|
remoteproc_cdsp: remoteproc@8300000 {
|
|
compatible = "qcom,sm8150-cdsp-pas";
|
|
reg = <0x0 0x08300000 0x0 0x4040>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
|
|
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
|
|
<&rpmhpd 7>;
|
|
power-domain-names = "load_state", "cx";
|
|
|
|
memory-region = <&cdsp_mem>;
|
|
|
|
qcom,smem-states = <&cdsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
|
|
label = "cdsp";
|
|
qcom,remote-pid = <5>;
|
|
mboxes = <&apss_shared 4>;
|
|
};
|
|
};
|
|
|
|
aoss_qmp: power-controller@c300000 {
|
|
compatible = "qcom,sm8150-aoss-qmp";
|
|
reg = <0x0 0x0c300000 0x0 0x100000>;
|
|
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apss_shared 0>;
|
|
|
|
#clock-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
spmi_bus: spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x0 0x0c440000 0x0 0x0001100>,
|
|
<0x0 0x0c600000 0x0 0x2000000>,
|
|
<0x0 0x0e600000 0x0 0x0100000>,
|
|
<0x0 0x0e700000 0x0 0x00a0000>,
|
|
<0x0 0x0c40a000 0x0 0x0026000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
cell-index = <0>;
|
|
};
|
|
|
|
remoteproc_adsp: remoteproc@17300000 {
|
|
compatible = "qcom,sm8150-adsp-pas";
|
|
reg = <0x0 0x17300000 0x0 0x4040>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
|
|
<&rpmhpd 7>;
|
|
power-domain-names = "load_state", "cx";
|
|
|
|
memory-region = <&adsp_mem>;
|
|
|
|
qcom,smem-states = <&adsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
|
|
label = "lpass";
|
|
qcom,remote-pid = <2>;
|
|
mboxes = <&apss_shared 8>;
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
|
|
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
apss_shared: mailbox@17c00000 {
|
|
compatible = "qcom,sm8150-apss-shared";
|
|
reg = <0x0 0x17c00000 0x0 0x1000>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
watchdog@17c10000 {
|
|
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
|
|
reg = <0 0x17c10000 0 0x1000>;
|
|
clocks = <&sleep_clk>;
|
|
};
|
|
|
|
timer@17c20000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x0 0x17c20000 0x0 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17c21000{
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x17c21000 0x0 0x1000>,
|
|
<0x0 0x17c22000 0x0 0x1000>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x17c23000 0x0 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x17c25000 0x0 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x17c26000 0x0 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x17c29000 0x0 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x17c2b000 0x0 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x17c2d000 0x0 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x0 0x18200000 0x0 0x10000>,
|
|
<0x0 0x18210000 0x0 0x10000>,
|
|
<0x0 0x18220000 0x0 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<CONTROL_TCS 0>;
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sm8150-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clock-names = "xo";
|
|
clocks = <&xo_board>;
|
|
};
|
|
|
|
rpmhpd: power-controller {
|
|
compatible = "qcom,sm8150-rpmhpd";
|
|
#power-domain-cells = <1>;
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp1 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp2 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp3 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp4 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp5 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l2: opp6 {
|
|
opp-level = <224>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp7 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp8 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp9 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp10 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp11 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@18323000 {
|
|
compatible = "qcom,cpufreq-hw";
|
|
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
|
|
<0 0x18327800 0 0x1400>;
|
|
reg-names = "freq-domain0", "freq-domain1",
|
|
"freq-domain2";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
|
|
#freq-domain-cells = <1>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|