mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 14:40:53 +07:00
f15cbe6f1a
This follows the sparc changes a439fe51a1.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/*
|
|
* include/asm-sh/cpu-sh3/cache.h
|
|
*
|
|
* Copyright (C) 1999 Niibe Yutaka
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*/
|
|
#ifndef __ASM_CPU_SH3_CACHE_H
|
|
#define __ASM_CPU_SH3_CACHE_H
|
|
|
|
#define L1_CACHE_SHIFT 4
|
|
|
|
#define SH_CACHE_VALID 1
|
|
#define SH_CACHE_UPDATED 2
|
|
#define SH_CACHE_COMBINED 4
|
|
#define SH_CACHE_ASSOC 8
|
|
|
|
#define CCR 0xffffffec /* Address of Cache Control Register */
|
|
|
|
#define CCR_CACHE_CE 0x01 /* Cache Enable */
|
|
#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
|
|
#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
|
|
#define CCR_CACHE_CF 0x08 /* Cache Flush */
|
|
#define CCR_CACHE_ORA 0x20 /* RAM mode */
|
|
|
|
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
|
|
#define CACHE_PHYSADDR_MASK 0x1ffffc00
|
|
|
|
#define CCR_CACHE_ENABLE CCR_CACHE_CE
|
|
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
|
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
|
#define CCR3_REG 0xa40000b4
|
|
#define CCR_CACHE_16KB 0x00010000
|
|
#define CCR_CACHE_32KB 0x00020000
|
|
#endif
|
|
|
|
#endif /* __ASM_CPU_SH3_CACHE_H */
|