mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 01:36:55 +07:00
2c32c65e37
On revisions of Cortex-A15 prior to r3p3, a CLREX instruction at PL1 may falsely trigger a watchpoint exception, leading to potential data aborts during exception return and/or livelock. This patch resolves the issue in the following ways: - Replacing our uses of CLREX with a dummy STREX sequence instead (as we did for v6 CPUs). - Removing the clrex code from v7_exit_coherency_flush and derivatives, since this only exists as a minor performance improvement when non-cached exclusives are in use (Linux doesn't use these). Benchmarking on a variety of ARM cores revealed no measurable performance difference with this change applied, so the change is performed unconditionally and no new Kconfig entry is added. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
||
---|---|---|
.. | ||
include/mach | ||
common.h | ||
exynos-smc.S | ||
exynos.c | ||
firmware.c | ||
headsmp.S | ||
hotplug.c | ||
Kconfig | ||
Makefile | ||
Makefile.boot | ||
mcpm-exynos.c | ||
mfc.h | ||
platsmp.c | ||
pm_domains.c | ||
pm.c | ||
pmu.c | ||
regs-pmu.h | ||
regs-sys.h | ||
sleep.S | ||
smc.h |